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609 results on '"Sciuto, Donatella"'

1. Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization

Author

Soldavini, Stephanie, Sciuto, Donatella, and Pilato, Christian

Subjects
Computer Science - Hardware Architecture
Abstract

Optimizing data movements is becoming one of the biggest challenges in heterogeneous computing to cope with data deluge and, consequently, big data applications. When creating specialized accelerators, modern high-level synthesis (HLS) tools are increasingly efficient in optimizing the computational aspects, but data transfers have not been adequately improved. To combat this, novel architectures such as High-Bandwidth Memory with wider data busses have been developed so that more data can be transferred in parallel. Designers must tailor their hardware/software interfaces to fully exploit the available bandwidth. HLS tools can automate this process, but the designer must follow strict coding-style rules. If the bus width is not evenly divisible by the data width (e.g., when using custom-precision data types) or if the arrays are not power-of-two length, the HLS-generated accelerator will likely not fully utilize the available bandwidth, demanding even more manual effort from the designer. We propose a methodology to automatically find and implement a data layout that, when streamed between memory and an accelerator, uses a higher percentage of the available bandwidth than a naive or HLS-optimized design. We borrow concepts from multiprocessor scheduling to achieve such high efficiency., Comment: Accepted for presentation at ASPDAC'23

Published
2022

3. Optimizing the Use of Behavioral Locking for High-Level Synthesis

Author

Pilato, Christian, Collini, Luca, Cassano, Luca, Sciuto, Donatella, Garg, Siddharth, and Karri, Ramesh

Subjects
Computer Science - Hardware Architecture, Computer Science - Cryptography and Security
Abstract

The globalization of the electronics supply chain requires effective methods to thwart reverse engineering and IP theft. Logic locking is a promising solution, but there are many open concerns. First, even when applied at a higher level of abstraction, locking may result in significant overhead without improving the security metric. Second, optimizing a security metric is application-dependent and designers must evaluate and compare alternative solutions. We propose a meta-framework to optimize the use of behavioral locking during the high-level synthesis (HLS) of IP cores. Our method operates on chip's specification (before HLS) and it is compatible with all HLS tools, complementing industrial EDA flows. Our meta-framework supports different strategies to explore the design space and to select points to be locked automatically. We evaluated our method on the optimization of differential entropy, achieving better results than random or topological locking: 1) we always identify a valid solution that optimizes the security metric, while topological and random locking can generate unfeasible solutions; 2) we minimize the number of bits used for locking up to more than 90% (requiring smaller tamper-proof memories); 3) we make better use of hardware resources since we obtain similar overheads but with higher security metric., Comment: Accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Published
2021
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5. ASSURE: RTL Locking Against an Untrusted Foundry

Author

Pilato, Christian, Chowdhury, Animesh Basak, Sciuto, Donatella, Garg, Siddharth, and Karri, Ramesh

Subjects
Computer Science - Cryptography and Security
Abstract

Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (IC) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed the semantic information into the netlist. We propose ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description. The RTL approach has three advantages: (i) it allows designers to obfuscate IP cores generated with many different methods (e.g., hardware generators, high-level synthesis tools, and pre-existing IPs). (ii) it obfuscates the semantics of an IC before logic synthesis; (iii) it does not require modifications to EDA flows. We perform a cost and security assessment of ASSURE., Comment: Accepted for publication in IEEE Transactions on VLSI Systems on 06-Apr-2021

Published
2020
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6. A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model

Author

Siracusa, Marco, Del Sozzo, Emanuele, Rabozzi, Marco, Di Tucci, Lorenzo, Williams, Samuel, Sciuto, Donatella, and Santambrogio, Marco Domenico

Subjects
Affordable and Clean Energy, Field programmable gate arrays, Optimization, Computational modeling, Analytical models, Estimation, Engines, Data models, Roofline performance model, FPGA, high-performance computing, hardware accelerator design, Computer Software, Distributed Computing, Computer Hardware, Computer Hardware & Architecture
Abstract

With reconfigurable fabrics delivering increasing performance over the years, Field-Programmable Gate Arrays (FPGAs) are becoming an appealing solution for next-generation High-Performance Computing (HPC) systems. However, in order to gain traction among traditional von Neumann architectures, the optimization process of Field-Programmable Gate Array (FPGA) designs should be further abstracted to a higher level. In fact, while High-Level Synthesis (HLS) already provides a handy way to write FPGA code with common high-level languages, substantial effort and expertise are still required to optimize the resulting FPGA design for the underlying hardware. To overcome this problem, we propose a semi-automated performance optimization methodology based on a Hierarchical Roofline model for FPGAs. System-wide and applications-specific optimizations such as off-chip memory transfer and data locality optimizations are guided by the FPGA Roofline model whereas FPGA-specific optimizations are automatically searched by a Design Space Exploration (DSE) engine. We demonstrate the way this methodology allows to easily analyze and optimize to peak system performance a wide set of applications ranging from particle methods, wavefront algorithms, and sparse arithmetic computations. In addition, we prove that the integrated Design Space Exploration (DSE) engine achieves a 14.36x maximum speedup if compared to previous automated solutions in the literature.

Published
2021

12. BuildingRules: A Trigger-Action Based System to Manage Complex Commercial Buildings

Author

Nacci, Alessandro, Balaji, Bharathan, Spoletini, Paola, Rana, Vincenzo, Gupta, Rajesh, Sciuto, Donatella, and Agarwal, Yuvraj

Abstract

Modern Building Management Systems (BMSs) provide limited amount of control to its occupants, and typically allow only the facility manager to set the building policies. In this context, we present BuildingRules, a system which provides an intuitive interface to the occupants of commercial buildings to customize their office spaces using trigger-action programming. BuildingRules automatically detects conflicts among the policies, expressed by the occupants, by using the Z3 SMT solver, and leverages an open source web service BMS (BuildingDepot) to provide access control and actuation services in a building. BuildingRules has been designed to scale for large commercial buildings, as it supports grouping of rooms for ease of policy expression, a scalable backend for resolving conflicts, and a simulator that shows the actuation of rules on a timeline. We tested our system with 23 users across 17 days in a virtual office building, and evaluate the effectiveness and scalability of BuildingRules.Pre-2018 CSE ID: CS2014-1008

Published
2014

20. Iris

Author

Soldavini, Stephanie, primary, Sciuto, Donatella, additional, and Pilato, Christian, additional

Published
2023
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23. Extensions of the hArtes Tool Chain

Author

Bettarelli, Ferruccio, Ciavattini, Emanuele, Lattanzi, Ariano, Beltrame, Giovanni, Ferrandi, Fabrizio, Fossati, Luca, Pilato, Christian, Sciuto, Donatella, Meeuws, Roel J., Ostadzadeh, S. Arash, Nawaz, Zubair, Lu, Yi, Marconi, Thomas, Sabeghi, Mojtaba, Sima, Vlad Mihai, Sigdel, Kamana, and Bertels, Koen, editor

Published
2012
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24. In Car Audio

Author

Cecchi, Stefania, Palestini, Lorenzo, Peretti, Paolo, Primavera, Andrea, Piazza, Francesco, Capman, Francois, Thabuteau, Simon, Levy, Christophe, Bonastre, Jean-Francois, Lattanzi, Ariano, Ciavattini, Emanuele, Bettarelli, Ferruccio, Toppi, Romolo, Capucci, Emiliano, Ferrandi, Fabrizio, Lattuada, Marco, Pilato, Christian, Sciuto, Donatella, Luk, Wayne, de Figueiredo Coutinho, Jose Gabriel, and Bertels, Koen, editor

Published
2012
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25. The hArtes Tool Chain

Author

Bertels, Koen, Lattanzi, Ariano, Ciavattini, Emanuele, Bettarelli, Ferruccio, Chiaradia, Maria Teresa, Nutricato, Raffaele, Morea, Alberto, Antola, Anna, Ferrandi, Fabrizio, Lattuada, Marco, Pilato, Christian, Sciuto, Donatella, Meeuws, Roel J., Yankova, Yana, Sima, Vlad Mihai, Sigdel, Kamana, Luk, Wayne, de Figueiredo Coutinho, Jose Gabriel, Ming Lam, Yuet, Todman, Tim, Michelotti, Andrea, Cerruto, Antonio, and Bertels, Koen, editor

Published
2012
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26. Emulating Transactional Memory on FPGA Multiprocessors

Author

Pusceddu, Matteo, Ceccolini, Simone, Tumeo, Antonino, Palermo, Gianluca, Sciuto, Donatella, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Berekovic, Mladen, editor, Fornaciari, William, editor, Brinkschulte, Uwe, editor, and Silvano, Cristina, editor

Published
2011
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35. Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs.

Author

SOZZO, EMANUELE DEL, CONFICCONI, DAVIDE, ZEN, ALBERTO, SALARIS, MIRKO, SCIUTO, DONATELLA, and SANTAMBROGIO, MARCO D.

Subjects
FIELD programmable gate arrays, SYSTEMS design
Abstract

Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications, embedded, and an emerging alternative for cloud-scale acceleration. However, FPGA adoption found limitations in their programmability and required knowledge. Therefore, researchers focused on FPGA abstractions and automation tools. Here, we survey three leading digital design abstractions: Hardware Description Languages (HDLs), High-Level Synthesis (HLS) tools, and Domain-Specific Languagess (DSLs). We review these abstraction solutions, provide a timeline, and propose a taxonomy for each abstraction trend: programming models for HDLs; Intellectual Property (IP)-based or System-based toolchains for HLS; application, architecture, and infrastructure domains for DSLs. [ABSTRACT FROM AUTHOR]

Published
2023
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36. Automatic Test Pattern Generation with BOA

Author

Gravagnoli, Tiziana, Ferrandi, Fabrizio, Lanzi, Pier Luca, Sciuto, Donatella, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Runarsson, Thomas Philip, editor, Beyer, Hans-Georg, editor, Burke, Edmund, editor, Merelo-Guervós, Juan J., editor, Whitley, L. Darrell, editor, and Yao, Xin, editor

Published
2006
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40. System Level Hardware–Software Design Exploration with XCS

Author

Ferrandi, Fabrizio, Lanzi, Pier Luca, Sciuto, Donatella, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, and Deb, Kalyanmoy, editor

Published
2004
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43. Hw/Sw Codesign of Embedded Systems

Author

Fornaciari, William, Sciuto, Donatella, Goos, Gerhard, editor, Hartmanis, Juris, editor, van Leeuwen, Jan, editor, González Harbour, Michael, editor, and de la Puente, Juan A., editor

Published
1999
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48. Protecting Hardware IP Cores During High-Level Synthesis

Author

Pilato, Christian, Sciuto, Donatella, Regazzoni, Francesco, Garg, Siddharth, and Karri, Ramesh

Subjects
IP protection, High-level synthesis, Hardware security, Obfuscation, Untrusted foundry, Integrated circuits
Published
2021

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