Search

Carriers are currently introducing 5G wireless systems at sub-6, 28, 38, 57–71, and 71–86 GHz. As 5G is commercially deployed, research into the next-generation communication systems (6G), expected to be 100–340 GHz, is beginning. Power-efficient systems operating at such high frequencies require RF front ends with transistor RF figures of merit (FOMs) such as transit frequency ${f}_{\tau}$ and maximum oscillation frequency ${f}_{\max}$ in excess of 500 GHz. Indium-phosphide (InP) heterojunction bipolar transistors (HBTs) and high-electron mobility transistors (HEMTs) are promising technologies for these extreme frequency applications.

A physics-based compact analytical formulation for the static drain current in heterojunction barrier (HB) carbon nanotube field-effect transistors is derived by incorporating the tunneling current through the barriers. This enables to capture the distinct curve shapes of device characteristics as compared to devices without HBs. For solving the Landauer integral a Gaussian-shaped surrogate function for the energy-dependent integrand is utilized. Moreover, the impact of multiple reflections between source and drain barrier is accounted for. The new formulation includes a smooth transition from thermionic emission-based transport in the subthreshold region to tunneling-dominated transport in the above-threshold regime.

This paper aims at determining RF operating limits of SiGe HBTs. Long-term stress tests consisting of RF large-signal stress and periodic measurements of small-signal parameters are performed. Reliable dynamic large-signal transistor operation is demonstrated beyond conventional static safe operating limits. In addition, RF operating limits are identified and degradation of SiGe HBTs accelerated by extreme RF stress is systematically characterized, analyzed and modeled. RF-stress-caused degradation is shown to significantly affect the collector current and demonstrated to be different from electrothermal breakdown caused by DC stress. A modeling approach for estimating SiGe HBT degradation under RF large-signal operating conditions is proposed and shown to agree very well with experimental data.

In this second part, the drain-current formulation for hetero-barrier (HB) carbon nanotube field-effect transistors (CNTFETs) is extended by considering the impact of phonon scattering along the channel. Computationally efficient expressions for the scattering-related transmission factor and the energy-averaged mean free path (MFP) are derived. Drain-induced barrier lowering (DIBL) is also accounted for in the model. The new drain-current formulation is then compared to data from both augmented drift diffusion (DD)–based device simulations of a CNTFET unit cell structure and measurements of multitube high-frequency (HF) CNTFETs. A dc Gummel symmetry test (GST) has been successfully performed.

Carbon nanotubes (CNTs) offer great potential for both high-integration digital and high-frequency applications due to their unique 1-D carrier transport properties. However, the typically large contact resistance between the source/drain metal and the metal-covered CNT prevents the advantages of CNTs from being exploited. For supporting process development toward lowering the contact resistance and also compact modeling of CNT field-effect transistors (CNTFETs), a method for extracting the contact resistance is proposed. By measuring at sufficiently high gate voltages and subsequent suitable extrapolation toward infinite gate voltage, the bias-dependent components of the total channel resistance can be eliminated to extract the contact resistance. The accuracy of the proposed method was first verified using device simulation and subsequently applied to fabricated CNTFETs. The proposed method is suitable for both single- and multitube CNTFETs as well as for capturing the statistical variation of the contact resistance across the wafer.

The overall purpose of this work (including Part I in this issue) is to demonstrate the physical modeling of InP/InGaAs double heterojunction bipolar transistors (DHBTs) using a deterministic Boltzmann transport equation (BTE) solver and an augmented drift-diffusion (aDD) solver. In this Part II, the BTE and aDD solver are applied to a DHBT technology, leveraging a physics-based HICUM/L2 compact model for extracting experimental reference data. To account for uncertainty in the device profile and material properties, a calibration method is employed for matching the simulation results to measurable electrical quantities of DHBTs. Although the two solvers produce comparable results for the terminal characteristics of the DHBT, the BTE simulations expose significant physical phenomena that cannot be captured by transport formulations relying on moments of the BTE.

The overall purpose of this work (including Part II in this issue) is to demonstrate the physical modeling of InP/InGaAs double heterojunction bipolar transistors (DHBTs) using a deterministic Boltzmann transport equation (BTE) solver, an augmented drift-diffusion (aDD) solver, and the HICUM/L2 compact model. This Part I introduces all tools that are employed for the simulations of DHBT structures in Part II and applies them to a GaAs $\text {n}^{+}\text {nn}^{+}$ sample structure for illustrating the calibration of the aDD solver by BTE results and physical effects that occur in such devices. After the calibration, aDD and BTE solvers are shown to produce comparable results.

The thermal resistance ${R}_{\text {th}}$ of SiGe heterojunction bipolar transistors (HBTs) is characterized and modeled at cryogenic temperatures up to room temperature (RT). A physics-based analytical solution for the thermal resistance has been derived for this wide temperature range. Two formulations including both chuck temperature and power dependence of ${R}_{\text {th}}$ have been developed and show good agreement with data from both 3-D thermal simulation and measurements.