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We report on electronic transport in dual-gate, artificially stacked bilayer graphene field effect transistors (BiGFETs) fabricated from large-area chemical vapor deposited (CVD) graphene. The devices show enhanced tendency to current saturation, which leads to reduced minimum output conductance values. This results in improved intrinsic voltage gain of the devices when compared to monolayer graphene FETs. We employ a physics based compact model originally developed for Bernal stacked bilayer graphene FETs (BSBGFETs) to explore the observed phenomenon. The improvement in current saturation may be attributed to increased charge carrier density in the channel and thus reduced saturation velocity due to carrier-carrier scattering.

Polarization-engineered Al0.2Ga0.8N channel heterostructure field-effect transistors (HFETs) with quaternary InAlGaN barrier layers have been investigated theoretically and numerically. The polarization-matched (PolM) normally-OFF InAlGaN/Al0.2Ga0.8N HFETs exhibited great breakdown characteristics, in which large breakdown voltage ( ${V}_{B}$ ) and highly efficient modulation of ${V}_{B}$ have been observed by varying the Al composition in the InAlGaN barrier. The electron drift velocity of approximately 1.1 $\times \,\,10^{{7}}$ cm/s, on par with that of the GaN channel HFETs, was achieved and become saturated in the Al0.2Ga0.8N channel of the InAlGaN/Al0.2Ga0.8N PolMHFETs when the ON-state drain bias operated in the current saturation region. Moreover, the electron saturation velocity of the InAlGaN/Al0.2Ga0.8N PolMHFETs showed a little deviation from that of an Al0.2Ga0.8N channel layer at high electric fields which was attributed to the carrier injection from the contacts neglected in the analytical model. As a result, superior RF power performance was obtained for the normally-OFF InAlGaN/Al0.2Ga0.8N PolMHFETs, according to the small- and large-signal simulation results. These findings highlight the advantages and potential of normally-OFF InAlGaN/AlGaN PolMHFETs for applications in high-frequency power electronics enabled by the alternative large ${V}_{B}$ without increasing the device dimension or Al composition in the AlGaN channel and high electron saturation velocity.

Gallium nitride (GaN) has found a unique role in the design of high-electron-mobility power devices due to its wide bandgap, high breakdown electric field, and appropriate saturation velocity. The main aim of this paper is to optimize the performance parameters of AlGaN/GaN high-electron-mobility transistors by optimizing the gate metal, the channel length, and the mole fraction of the AlGaN layer. The main objective of this performance optimization is to increase the on-state current, improve the ION/IOFF ratio, and increase the threshold voltage of the transistor. The results show that the transistor with a 3-nm barrier layer (AlGaN) and 5-nm HfLaO gate oxide exhibits an on-state current of 304 mA and an ION/IOFF ratio o f 11.4 × 1014 at VGS = 4 V, corresponding to a threshold voltage (Vth) of 1.39 V.

In this article, we present a surface-potential-based approach to model the bias-dependent effective velocity observed in AlGaN/GaN high-electron-mobility transistors (HEMTs) due to optical phonon scattering. Our model precisely reproduces the progressive decrease in the saturation velocity in GaN HEMTs with increasing gate voltages, as reported in the literature, which is predominantly due to the scattering of electrons, forming the high-density two-dimensional electron gas (2DEG), by optical phonons at high overdrive voltages. We show that this dependence differs from the traditional mobility degradation models in terms of its impact on the device current–voltage ( ${I}$ – ${V}$ ) characteristics and illustrate how the inclusion of a velocity saturation model also provides the model users with an additional handle for parameter extraction. The model is explicit and, by virtue of its Simulation Program with Integrated Circuit Emphasis (SPICE) compatibility, is readily implemented in the industry-standard Advanced SPICE Model for HEMTs (ASM-HEMTs) model and has been validated against experimental dc ${I}$ – ${V}$ and RF S-parameter measurements of an in-house GaN device.

The development of next-generation wireless communication technology requires integrated radiofrequency devices capable of operating at frequencies greater than 90 GHz. Carbon nanotube field-effect transistors are promising for such applications, but key performance metrics, including operating frequency, at present fall below theoretical predictions. Here we report radiofrequency transistors based on high-purity carbon nanotube arrays that are fabricated using a double-dispersion sorting and binary liquid interface aligning process. The nanotube arrays exhibit a density of approximately 120 nanotubes per micrometre, a maximum carrier mobility of 1,580 cm2 V−1 s−1 and a saturation velocity of up to 3.0 × 107 cm s−1. The resulting field-effect transistors offer high d.c. performance (on-state current of 1.92 mA µm−1 and peak transconductance of 1.40 mS μm−1 at a bias of −0.9 V) for operation at millimetre-wave and terahertz frequencies. Transistors with a 50 nm gate length show current-gain and power-gain cutoff frequencies of up to 540 and 306 GHz, respectively, and radiofrequency amplifiers can exhibit a high power gain (23.2 dB) and inherent linearity (31.2 dBm output power of the third-order intercept point) in the K-band (18 GHz). Transistors based on arrays of aligned carbon nanotubes can exhibit cutoff frequencies of up to 540 GHz, and could be further scaled for operation at millimetre-wave and terahertz frequencies.

We report the positive effects of SiC substrate thinning on the DC and RF performance of AlGaN/GaN high electron mobility transistors (HEMTs). The substrate is thinned down from 500 to $\sim 100~\mu \text{m}$ . This leads to a strain redistribution at the AlGaN/GaN interface confirmed through X-ray diffraction measurements. The contact resistance decreases significantly. The two-dimensional electron gas (2DEG) density decreases, and mobility increases in the source/drain access regions from reduced polarization. The decrease in 2DEG dominates, leading to an increase in the sheet resistance. An opposite trend is manifested in the channel region below the gate contact. The increase in mobility and saturation velocity dominates the decrease in the 2DEG density, which is minimal. The channel resistance decreases. The combined effects of contact, access, and channel regions are further investigated and verified in high-performance AlGaN/GaN HEMTs. The ON-resistance decreases, and saturation drain current increases substantially. The RF performance in critical parameters, including unity-current gain frequency (fT), gain, and output power density, increases significantly. The disparate effects of the contact, access, and channel regions are used in a calibrated TCAD simulator, which shows consistent HEMT performance improvements as observed experimentally.

The high-frequency performance of top-gated graphene field-effect transistors (GFETs) depends to a large extent on the saturation velocity of the charge carriers, a velocity limited by inelastic scattering by surface optical phonons from the dielectrics surrounding the channel. In this work, we show that, by simply changing the graphene channel surrounding dielectric with a material having higher optical phonon energy, one could improve the transit frequency and maximum frequency of oscillation of GFETs. We fabricated GFETs on conventional SiO2/Si substrates by adding a thin Al2O3 interfacial buffer layer on top of SiO2/Si substrates, a material with about 30% higher optical phonon energy than that of SiO2, and compared performance with that of GFETs fabricated without adding the interfacial layer. From S-parameter measurements, a transit frequency and a maximum frequency of oscillation of 43 and 46 GHz, respectively, were obtained for GFETs on Al2O3 with 0.5- $\mu \text{m}$ gate length. These values are approximately 30% higher than those for state-of-the-art GFETs of the same gate length on SiO2. For relating the improvement of GFET high-frequency performance to improvements in the charge carrier saturation velocity, we used standard methods to extract the charge carrier velocity from the channel transit time. A comparison between two sets of GFETs with and without the interfacial Al2O3 layer showed that the charge carrier saturation velocity had increased from $1.5\cdot 10^{{7}}$ to $2\cdot 10^{{7}}$ cm/s.

This paper presents the novel normally-on dual gate (DG) AlGaN/GaN high electron mobility transistor. At high frequency, the dual gate structure gives superlative immunity over short channel effects. Multiple 2DEG channel regions in dual gate AlGaN/GaN HEMT improves the transport characteristics, charge control and gives better linearity. The high carrier mobility and electron saturation velocity contribute to the high switching frequency of DG HEMT. The drain characteristics of single gate HEMT and dual gate HEMT are compared and DG HEMT outstands in drain current. The various analog and linearity parameters are investigated for DG HEMT. The performance analysis provides better transconductance, capacitance, cut off frequency, subthreshold slope and on-resistance simulations represents the potential of DG HEMT. The DG HEMT provides 1100 mA/mm ION, 550 mS/mm transconductance and 11 GHz cutoff frequency at Vgs = 2 V. The high drain current, better transconductance and cutoff frequency results in better sensitivity of device.

This paper presents the calibration of the novel kinetic velocity model (KVM) in the drift-diffusion (DD) transport approach, which can account for the ballistic effect in short-channel devices. The KVM considers a thermionic emission limit and a free carrier acceleration limit for the mobility. We develop a methodology to extract the parameters for the KVM and for the high-field saturation velocity model for SiGe nanowires over the whole mole fraction range. The calibrated DD simulations with KVM show good agreement with Boltzmann transport equation results in terms of on-state current and carrier-weighted velocity distribution over a wide range of gate lengths for both linear and saturation regimes.

In this paper, the influences of channel transport on the output characteristic in sub-100nm heterojunction tunnel FET have been investigated through TCAD simulation. The calibrated tunneling and transport parameters with experiment have been adopted. The influences of the parameters characterizing channel transport, i.e., mobility, channel length, and saturation velocity, are analyzed in detail under different biases. It is found that the channel transport has stronger impact on the performance of the device biased in the linear region and with smaller mobility, longer channel, and higher saturation velocity. The saturation drain voltage can be reduced by improving the mobility and reducing the saturation velocity. However, the latter will reduce the current simultaneously. What’s more, considering quantum confinement, the variation in performance of the device induced by the change of mobility is still visible after some optimization strategies are used.

When the gated channel region of a GaN high-electron-mobility transistor (HEMT) is configured into multiple sub-channels in parallel and separated by embedded isolating patterns, the effective resistance of the access regions could be reduced, and consequently, the knee voltage ( ${V}_{{\text {K}}}$ ) of the transistor could be lowered. In this work, each sub-channel is defined as a convergent funnel-like shape, with its width gradually shrunk from the source side to the drain side. Different from conventional channels with uniform width under the entire gate, the funnel-shaped channel could converge electrons as they transport from source side to drain side, which facilitates electrons’ acceleration toward saturation velocity under a smaller drain-to-source bias, leading to a reduced intrinsic ${V}_{{\text {K}}}$ in the gated channel. Thus, more desirable ${I}$ - ${V}$ characteristics and more balanced performance enhancement in RF linearity and power added efficiency are achieved at a low supply voltage, making the convergent-channel HEMT attractive for power amplifiers in mobile terminals.

It has been shown that there can be a significant temperature increase in graphene field-effect transistors (GFETs) operating under high drain bias, which is required for power gain. However, the possible effects of self-heating on the high-frequency performance of GFETs have been weakly addressed so far. In this article, we report on an experimental and theoretical study of the effects of self-heating on dc and high-frequency performance of GFETs by introducing a method that allows accurate evaluation of the effective channel temperature of GFETs with a submicrometer gate length. In the method, theoretical expressions for the transit frequency ( ${f}_{\text {T}}$ ) and the maximum frequency of oscillation ( ${f}_{\text {max}}$ ) based on the small-signal equivalent circuit parameters are used in combination with the models of the field- and temperature-dependent charge carrier concentration, velocity, and saturation velocity of GFETs. The thermal resistances found by our method are in good agreement with those obtained by the solution of the Laplace equation and by the method of thermo-sensitive electrical parameters. Our experiments and modeling indicate that the self-heating can significantly degrade the ${f}_{\text {T}}$ and ${f}_{\text {max}}$ of GFETs at power densities above 1 mW/ $\mu \text{m}^{2}$ , from approximately 25 to 20 GHz. This article provides valuable insights for further development of GFETs, taking into account the self-heating effects on the high-frequency performance.

Gallium nitride (GaN) offers high electron mobility, breakdown voltage and saturation velocity, and is an ideal candidate for advanced electronic and power devices. Meanwhile, it can also be used for microelectromechanical systems (MEMS) and micro/nano-mechanical devices. These applications fundamentally rely on its mechanical properties and structural reliability, in particular at the micro/nanoscale. In this paper, single crystalline [0001]-oriented GaN pillars with diameters ranging from ∼200 nm to ∼1.5 μm were microfabricated and systematically characterized by in situ compression tests inside a SEM/TEM at room temperature. It showed that a crack would nucleate at the top of the pillars with diameters800 nm and propagate axially during compression. However, pillars with diameters less than 700 nm would deform plastically without splitting, with maximum stress up to 10 GPa. The corresponding yield/fracture strengths show a strong size effect, which increases from ∼4 GPa to ∼11 GPa with the diameter decreasing from ∼1.5 μm to ∼400 nm. In situ TEM compression tests suggest that the formation of slip bands on the (01[combining macron]11) plane dominates the plastic deformation of the pillars with diameters of ∼200-700 nm, while both crack splitting and slip bands were observed in the pillars with diameters around 700 to 800 nm during the brittle-to-ductile transition. This work provides critical insights for developing robust GaN-based MEMS and power electronic applications.

Conventional pseudomorphic high electron mobility transistor (pHEMTs) with lattice-matched InGaAs/InAlAs/InP structures exhibit high mobility and saturation velocity and are hence attractive for the fabrication of three-terminal low-noise and high-frequency devices, which operate at room temperature. The major drawbacks of conventional pHEMT devices are the very low breakdown voltage (xGa(1−x)As (x = 0.53 or 0.7) channel material plus the contribution of other parts of the epitaxial structure. The capability to achieve higher frequency operation is also hindered in conventional InGaAs/InAlAs/InP pHEMTs, due to the standard 1 μm flat gate length technology used. A key challenge in solving these issues is the optimization of the InGaAs/InAlAs epilayer structure through band gap engineering. A related challenge is the fabrication of submicron gate length devices using I-line optical lithography, which is more cost-effective, compared to the use of e-Beam lithography. The main goal for this research involves a radical departure from the conventional InGaAs/InAlAs/InP pHEMT structures by designing new and advanced epilayer structures, which significantly improves the performance of conventional low-noise pHEMT devices and at the same time preserves the radio frequency (RF) characteristics. The optimization of the submicron T-gate length process is performed by introducing a new technique to further scale down the bottom gate opening. The outstanding achievements of the new design approach are 90% less gate current leakage and 70% improvement in breakdown voltage, compared with the conventional design. Furthermore, the submicron T-gate length process also shows an increase of about 58% and 33% in fT and fmax, respectively, compared to the conventional 1 μm gate length process. Consequently, the remarkable performance of this new design structure, together with a submicron gate length facilitatesthe implementation of excellent low-noise applications.

This paper discusses different parameters and their effects on the efficiency of a crystalline solar cell. This is done using a 1D Drift Diffusion model for silicon solar cells by varying several parameters like the n-layer and p-layer thickness, electron and hole doping concentration, the electron and hole maximum SRH lifetime, and electron-hole saturation velocity. A various permutation of the values of these parameters was used to study various characteristics of the solar cell and calculate the maximum efficiency. It investigated various output characteristics to understand the correlation between these input parameters and the efficiency of solar cells. Simulating graphs such as current and power vs voltage, band diagrams helped us in getting optimum input parameters to achieve maximum efficiency. The paper presents, as motivation for this work, a number of parameters that can be used to increase the efficiency of a solar cell, which is a fundamental unit of a solar panel, which in turn can be a stepping stone to move towards a cleaner energy source. The efficiency of the solar cell peaked when the n-layer and p-layer thickness took $3\ \mu \mathrm{m}$ and $55\ \mu \mathrm{m}$ values respectively, while the ideal SRH lifetime for a crystalline silicon solar cell was measured to be 10−2 s. The efficiency achieved for the same was 24.61%. This paper further explores and understands the reasons for these optimums and how and by how much they improve the efficiency of the solar cell.

With incredibly high carrier mobility and saturation velocity, graphene would be an ideal candidate for a miniaturized solid-state cyclotron radiation source. A planar semicircular graphene arc geometry was investigated for emission in the 0.5–1.5 THz range. Analytical studies, confirmed by finite element simulations, show that the emitted THz frequencies are inversely proportional to the arc radius given a fixed charge-carrier velocity. The simulations show that the desired frequency spectrum can be obtained with design radii ranging from 50 to 150 nm. Interestingly, the radiated spectrum is independent of the frequency of the stimulation of the graphene nano-arcs. The simulations also indicate that the total output power correlates well with the Larmor formulation. The device is expected to emit 1 nW/cm2, which confirms the findings of existing research in this field. Such a design could yield a scalable and cost-effective THz source.

A drain current model based on Lambert W function is analyzed for lightly doped (undoped) short channel tri gate FinFET (TG-FinFET). The channel length modulation (CLM), the effect of series resistance, mobility degradation and saturation velocity are included in the drain current model. Quantum mechanical effect (QME) is also included to achieve precise drain current for such a small channel device. The model is inspected mainly for two fin widths with two dielectric materials namely, silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 ). A complete study of electrical parameters including surface potential and the threshold voltage are addressed for both the dielectric materials. The threshold voltage is cross-examined by reported experimental results.

In recent years, new efficient power devices have been implemented. Silicon Carbide has replaced silicon as regards the production and the utilization of many devices, such as MOSFETs, diodes, IGBTs and many others. SiC devices are characterized by a low reverse recovery charge, high carrier saturation velocity, by which it is possible to work at high frequency, and high breakdown voltage. Thanks to the great thermal conductivity and the wide bandgap, these devices can operate at high temperature and reach high voltages and currents. What is important to stress is the fact that power losses in SiC devices are lower than the silicon ones. These are the reasons why these devices are utilized in a wide range of technological applications, including power electronics. In this paper, power losses in Si and SiC devices are evaluated in simulation and compared to each other. In order to demonstrate the remarkable advantages of the SiC devices over the silicon ones, a study which makes use of an isolated DC-DC converter has been conducted. As regards the proposed full-bridge converter, SiC and silicon MOSFETs and diodes, of whom some static and dynamic parameters are defined, are used in order to transfer power from a DC voltage supply to a load.

Gallium nitride (GaN) high-electron-mobility transistor (HEMT) and vertical GaN metal-oxide-semiconductor (MOS) devices have potential application to high power and high frequency because of their superior characteristics, such as wide band gap (B g ), high electron saturation velocity, and a high critical breakdown voltage [ 1 – 3 ]. Gate insulator plays an important role to suppress the leakage current in both GaN HEMT and GaN MOS devices. Various materials such as SiO 2 , Al 2 O 3 , HfO 2 , AlSiO x , and HfSiO x have been widely investigated as gate insulator, and films of these materials are typically deposited via chemical vapor deposition or atomic layer deposition (ALD) [ 4 – 10 ]. Figure 1 shows the relationship between dielectric constant ( k ) and B g of candidate gate insulators [11] . The B g generally decreases as the k value increases. HfO 2 is known to have a high k value but crystallization temperature is as low as 400°C. Al 2 O 3 starts to crystalize around 700°C. On the other hand, silicate materials such as AlSiO x and HfSiO x have a more stable amorphous structure at 800°C and expect to suppress the leakage current. Here, AlSiO x and HfSiO x films were formed by a two-step process such as film formation of (Al 2 O 3 ) m /(SiO 2 ) n and (HfO 2 ) m /(SiO 2 ) n nanolaminate structures using ALD, respectively, and post-deposition annealing (PDA) treatment.

This study presents a photo-assisted method to measure the drift velocity of carriers in semiconductors, and successfully used to determine the drift velocity of holes in GaN. A p-i-n diode with a buried p-type layer was designed and fabricated on a free-standing GaN substrate. By reverse-biasing the p-i-n diode and illuminating the cathode layer using an ultraviolet light simultaneously, photo-generated holes were injected into the depletion region and accelerated by the electric field to reach the saturation velocity. The drift velocity ( $\text{v}_{\text {d}}$ )–electric field (E) characteristic can be obtained from the photocurrent induced by photo-generated holes. The measured hole drift velocity can be written as $v_{\text {d}}=\mu _{\text {LF}}E /[1+(\mu _{\text {LF}}E/v_{{\mathrm {sat}}})^{{\beta }}]^{{1}/\beta }$ , where $\mu _{\text {LF}}\,\,=17$ cm2/Vs is the low-field hole mobility, $v_{\text {sat}}= 6.63\times 10^{{6}}$ cm/s is the saturation velocity, $\beta =1.75$ is the fitting parameter. The method presented in this study is a unique way of determining the saturation drift velocity of holes in GaN.