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A 5 bit sample-and-hold less pipelined ADC is presented for high speed and low power applications. The architecture is designed using 32nm CNFET model in Hspice and simulation is carried out at 10 GSPS sampling rate. From the simulation results, the SNDR is found out to be 32.89dB at Nyquist frequency and the ERBW is found to be 3GHz from 2 to 5GHz in which ENOB is guaranteed to be above 4.6. The average power consumed is 5.031mW for a supply voltage of 1.4V and FoM is 53.32fJ/step.

The Scaling of conventional Complementary Metal Oxide Semiconductors (CMOSs) has been facing problems such as short channel effect due to hot electron effect and leakage power. Fin Field Effect Transistor (FinFET) is considered as solution to this issue. Binary system occupies large area there for the circuit complexity is increasing on a VLSI chip and thus degrading the performance of binary system. Multi valued logic MVL is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip I have designed FinFET based ternary basic gates (T-NOT, ST-NAND, ST-NOR, ST-AND and ST-OR). FinFET is classified in to two types based on gate structure: 1) Short Gate FinFET (SG-FinFET) and 2) Independent Gate FinFET (IG-FinFET). The proposed ternary logic gates are design using SG-FinFET. Simulation is performed with Tanner EDA tool. The proposed design has achieved good reduction in the circuit element count.

Multi Valued Logic [MVL] has experienced major evolution in the recent past due to several advantages offered by them over the binary logic. Ternary Logic (a logic with radix 3 i.e. 3 logic states) is a promising alternative to the binary logic making it a thrust area of research. With the recent technological advancements, commercial realization of ternary circuits is watched with keen interests thereby attracting the attention of wide community of researchers to explore the usability of various alternative devices for implementing ternary circuits. This research proposes a novel hybrid approach based on combination of MIFGMOS (Multi Input Floating Gate Metal Oxide Semiconductor) transistor and conventional MOSFET for the realization of the ternary gates. In a digital system, NOT, NAND and NOR are of more importance as they are the building blocks of many other complex logic and arithmetic circuits. In this paper, the designs (based on hybrid combination of devices) of two input TNAND and TNOR gates are detailed which along with MIFGMOS transistor based T-inverter are further used to design TAND, TOR, TXOR and TXNOR gates. An extensive simulation of all the designed gates is carried out using TSPICE circuit simulator. The results demonstrate expected functionality of the proposed hybrid gates and additionally signify improvement in the performance parameters. The proposed hybrid approach combines the virtues of both the devices which facilitate the significant reduction in the circuit element count of the ternary gates as compared to earlier reported methods.

Valued Logic (MVL) is emerging as a promising choice for future computing technology. MVL has seen major advancement in the recent past due to several advantages offered by them over the binary logic, thus making it a thrust area for further research. The instruction set of the processor is its inherent entity. This paper presents design and implementation of an efficient instruction set for a ternary processor using Very-High-Speed Integrated Circuits, VHSIC Hardware Description Language (VHDL). Twenty one instructions including various addressing modes such as register, direct and immediate mode are designed and implemented for 4-trit ternary processor. The required control signals are appropriately identified in the proposed design and enable the smooth operation of instructions. The designed 4 - trit instruction set signifies encouraging results that will pave the path for further developments in ternary processors.

With the scenario of today, everybody using internet, net banking, and online shopping. Nowadays people having smart phone, palm top with latest updated operating system like windows 10, android. These gadgets are using as G.P.S., pocket banking, gaming, notepad, reminder and lot of ways. The most and very important thing is security. To fulfill this important requirement the efficient way is Encryption Decryption algorithm. But another point is speed means algorithm which would be efficient and fast. In order to achieve this requirement, different algorithms have been designed and implemented in the past, but every algorithm possess their own shortcomings with respect to an ASIC or an FPGA implementation. In this paper, I proposed and implemented of a one very useful method for area efficient and high performance for AES by using “Mixing of column and Inverse mixing of column operation” which is the one of the major block of operation in AES to implement the high performance of AES. I SIMULATE and SYNTHESIS on XILINX ISE 14.7 and implemented on VIRTEX 4. It is 100% area efficient; I compared my result with other. With this implementation I given the different methods for s-box and another methods to implement the mixing of column and inverse mixing of column.

The Scaling of conventional CMOSs (Complementary Metal Oxide Semiconductors) has been facing problems such as short channel effect due to hot electron effect and leakage power. To solve the problems, FinFETs (Fin Field Effect Transistor) device structures are solution. Binary System occupies large area there for the circuit complexity is increasing on a VLSI chip and thus, degrading the performance of binary system. MVL (Multi valued logic) is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip, we have designed ternary Static Random Access Memory (SRAM) Cell using Shorted Gate FinFET (SG-FinFET). FinFET is double gate transistor architecture to extend scaling over planar device. Two gates have better control over the short channel effects. The paper presents a novel design of 6 Transistor ternary SRAM cell, with separate read and write lines. The proposed SRAM cell designed using Tanner tool version 13 and simulated with the help of W-Edit version 13.

Ternary logic has been evolved from binary logic due to its many advantages as it is energy efficient, less complex and faster speed for serial transfer. Due to these technological advancements ternary circuits have attracted many researchers to implement ternary circuits. In digital system, NOT, NOR and NAND are of importance as they are the main building blocks of many complex arithmetic and logic circuits. In this paper, we discuss the basic ternary gates and some circuits implemented by using FinFET. An extensive simulation is performed for all the gates and circuits using Tspice Simulator. FinFET is being adapted instead of traditional MOSFET because of its captivity over the drawbacks occurred during narrowing to nanometer scale. Results obtained have expected functionality of each gate and circuits, additionally there is enhancement in performance parameters.

Inthis paper we present the ternary logic gates implementation using FGMOS (Floating gate MOSFET) also calledMIFG MOSFET (Multi input floating gate MOSFET). Implementation using ternary logic have advantage than binary logic implementation in terms of more information capability, reduced interconnections and reduction in chip area. MIFG MOSFETs design reduces transistor count as a result area of chip will reduce. Ternary logic gates using MIFG MOSFETs reduces transistor count compared with CMOS design and CNTFET based designs.

This paper presents a novel design of ternary D-latch using carbon nanotube field effect transistors. Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. In this paper novel design of D-latch for ternary logic based on CNTFET, using only basic gates STI, NTI, NOR, NAND and transmission gate, is proposed.

A new era of digital computation investigates the advantages of non-binary machine logic over the conventional binary logic. Multi Valued Logic [MVL] systems, where the radix is greater than 2 are evolving as a thrust area of research. Ternary logic has gained wide popularity and offers several potential opportunities for the improvement of present VLSI circuit designs. Ternary gates form the fundamental element for numerous ternary circuits, making its efficient design and simulation indispensable. This paper presents the implementation and simulation of ternary gates (TNOT, TNAND, TNOR) using injected voltage method. The binary CMOS logic is exploited to achieve the ternary logic values. The performance analysis of the ternary gates in terms of rise time, fall time and power dissipation is examined using Tanner Tool, version 13.02. The prominent subsets (S-Edit, L-Edit, T-Spice and W-Edit) of the tanner tool are used to derive the various device parameters and further verify the functionality of the gates. The layouts of the designed gates are also presented.

The design of a high Gain microstrip patch antenna array using microstrip line feed is presented in this paper. The design has been done for C band application at 5.81GHz for Rainfall RADAR also called as Precipitation Occurrence Sensor System (POSS). Array consisting of 16 elements of 4×4 were designed and simulated using HFSS v13 on Taconic TLY substrate of dielectric constant 2.2 and height of substrate equal to 1.58 mm. For the proposed antenna, the achieved gain is 19.5 dBi, return loss is ≤ 30 dB, 3 dB bandwidth of 170 MHz with low side lobes and back lobe. The Array antenna was excited by uniform amplitude and phase feeding method. A comparative analysis was done between 1×2, 2×2 and 4×4 array. It was found that gain increases at cost of bandwidth.