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Synthetic analog gene circuits can be engineered to execute logarithmically linear sensing, addition, ratiometric and power-law computations in living cells using just three transcription factors. Living-cell computation simplified The design of novel genetic control systems for synthetic biology is dominated by digital logic. This is necessarily a complex arrangement. Now Timothy Lu and colleagues have harnessed analog building-blocks found in natural cells to perform arithmetic operations in the logarithmic domain. Such analog circuits -- which could be integrated with digital -- should make it possible to use fewer components to implement complex computations that require wide dynamic range in biosensing. A central goal of synthetic biology is to achieve multi-signal integration and processing in living cells for diagnostic, therapeutic and biotechnology applications.sup.1. Digital logic has been used to build small-scale circuits, but other frameworks may be needed for efficient computation in the resource-limited environments of cells.sup.2,3. Here we demonstrate that synthetic analog gene circuits can be engineered to execute sophisticated computational functions in living cells using just three transcription factors. Such synthetic analog gene circuits exploit feedback to implement logarithmically linear sensing, addition, ratiometric and power-law computations. The circuits exhibit Weber's law behaviour as in natural biological systems.sup.4, operate over a wide dynamic range of up to four orders of magnitude and can be designed to have tunable transfer functions. Our circuits can be composed to implement higher-order functions that are well described by both intricate biochemical models and simple mathematical functions. By exploiting analog building-block functions that are already naturally present in cells.sup.3,5, this approach efficiently implements arithmetic operations and complex functions in the logarithmic domain. Such circuits may lead to new applications for synthetic biology and biotechnology that require complex computations with limited parts, need wide-dynamic-range biosensing or would benefit from the fine control of gene expression., Author(s): Ramiz Daniel [sup.1] [sup.2] [sup.3] , Jacob R. Rubens [sup.2] [sup.3] [sup.4] , Rahul Sarpeshkar [sup.1] [sup.3] [sup.4] [sup.5] [sup.6] [sup.7] , Timothy K. Lu [sup.2] [sup.3] [sup.4] [sup.5] [...]

We present a bidirectional MOS resistor circuit that is electronically tunable and has zero dc offset. For a given I-V characteristic, the circuit senses the source-to-drain potential across an MOS device and automatically generates an appropriate bias for the gate terminal to implement the characteristic via negative feedback. We show that the I-V characteristic of the resistor can be designed to be linear, compressive or expansive by using appropriate translinear current mode circuits for the feedback biasing. Our technique does not require the MOS transistor to operate in the triode region and is valid in both weak and strong inversion. Experimental results from a CMOS process show that a square-root, linear, or square resistor can be implemented as examples of our topology. The linear version was tunable over a resistance range of 1 M[ohm]-100 G[ohm] in our particular implementation and exhibited proportional-to-absolute temperature (PTAT) behavior. The measured excess noise of the resistor agrees with theoretical predictions. Index Terms--Bulk-referenced model, electronically tunable resistor, MOS resistor, nonlinear resistor.

We investigate theoretical and practical aspects of the design of far-field RF power extraction systems consisting of antennas, impedance matching networks and rectifiers. Fundamental physical relationships that link the operating bandwidth and range are related to technology dependent quantities like threshold voltage and parasitic capacitances. This allows us to design efficient planar antennas, coupled resonator impedance matching networks and low-power rectifiers in standard CMOS technologies (0.5-[micro]m and 0.18-[micro]m) and accurately predict their performance. Experimental results from a prototype power extraction system that operates around 950 MHz and integrates these components together are presented. Our measured RF power-up threshold (in 0.18-[micro]m, at 1 [micro]W load) was 6 [micro]W [+ or -] 10%, closely matching the predicted value of 5.2 [micro]W. Index Terms--Antennas, circuit theory, CMOS analog integrated circuits, rectifiers.

Cochlear implants currently fail to convey phase information, which is important for perceiving music, tonal languages, and for hearing in noisy environments. We propose a bio-inspired asynchronous interleaved sampling (AIS) algorithm that encodes both envelope and phase information, in a manner that may be suitable for delivery to cochlear implant users. Like standard continuous interleaved sampling (CIS) strategies, AIS naturally meets the interleaved-firing requirement, which is to stimulate only one electrode at a time, minimizing electrode interactions. The majority of interspike intervals are distributed over 1-4 ms, thus staying within the absolute refractory limit of neurons, and form a more natural, pseudostochastic pattern of firing due to complex channel interactions. Stronger channels are selected to fire more often but the strategy ensures that weaker channels are selected to fire in proportion to their signal strength as well. The resulting stimulation rates are considerably lower than those of most modern implants, saving power yet delivering higher potential performance. Correlations with original sounds were found to be significantly higher in AIS reconstructions than in signal reconstructions using only envelope information. Two perceptual tests on normal-hearing listeners verified that the reconstructed signals enabled better melody and speech recognition in noise than those processed using tone-excited envelope-vocoder simulations of cochlear implant processing. Thus, our strategy could potentially save power and improve hearing performance in cochlear implant users. Index Terms--Asynchronous stimulation, cochlear implant, neural stimulation, phase information.

There is an increasing trend in several biomedical applications such as pulse-oximetry, ECG, PCG, EEG, neural recording, temperature sensing, and blood pressure for signals to be sensed in small portable wireless devices. Analog-to-digital converters (ADCs) for such applications only need modest precision ([less than or equal to] 8 bits) and modest speed ([less than or equal to] 40 kHz) but need to be very energy efficient. ADCs for implanted medical devices need micropower operation to run on a small battery for decades. We present a bin-inspired ADC that uses successive integrate-and-fire operations like spiking neurons to perform analog-to-digital conversion on its input current. In a 0.18-[micro]m subthreshold CMOS implementation, we were able to achieve 8 bits of differential nonlinearlity limited precision and 7.4 bits of thermal-noise-limited precision at a 45-kHz sample rate with a total power consumption of 960 nW. This converter's net energy efficiency of 0.12 pJ/quantization level appears to be the best reported so far. The converter is also very area efficient (< 0.021 [mm.sup.2]) and can be used in applications that need several converters in parallel. Its algorithm allows easy generalization to higher speed applications through interleaving, to performing polynomial analog computations on its input before digitization, and to direct time-to-digital conversion of event-based cardiac or neural signals. Index Terms--Analog-digital (A/D), bio-inspired, energy efficient, successive subranging, time based, time to digital.

Jump resonance is a phenomenon where smooth changes in the input of a nonlinear filter lead to abrupt changes in its output. For over 50 years, research has defined the region of operation where jump resonance can occur so that this region may be avoided by limiting the signal amplitude of operation. This paper provides an intuitive understanding of jump resonance and predicts the behavior of the system in the jump resonance regime. This allows for further tradeoffs between system behavior and power consumption for highly power-efficient filtering systems. Our technique is verified against experimental data. Then we present a system that gracefully adapts its quality factor, avoiding jump resonance in a way qualitatively similar to biology. Finally, we demonstrate an integrated circuit realization. Index Terms--Adaptive-Q, Fukuma-Matsubara, [G.sub.m]-C filter, jump resonance, low power.

We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-[micro]m BiCMOS technology with a power consumption of 211 [micro]W and 77-dB dynamic range of operation. The 9.58 mm x 9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (A/D)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear-implant systems of the future which require decades of operation on a 100-mAh rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 [micro]W power consumption of a JFET-buffered electret microphone and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77-dB input dynamic range into a narrower internal dynamic range (IDR) of 57 dB at which each of the 16 spectral channels of the processor operate. The output bits of the processor are scanned and reported off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits ensure robust operation of the processor in the high-RF-noise environment typical of cochlear implant systems. Index Terms--Bionic ear, cochlear implant, hearing aids, low power, spectrum analysis, speech recognition.

We describe an architecture that adds a linear predictor and adaptive control to a comparator to greatly reduce its delay. The linear predictor feeds an estimated future signal to the comparator to compensate for the comparator's inherent delay. On a cycle-by-cycle basis, an adaptive controller adjusts the comparator's bias current to null residual errors that remain after the prediction. Emphasis is placed on low power consumption, including the development of a linear predictor with no static power consumption. In an experimental 1.5-[micro]m VLSI chip implementation, our scheme enabled a 45-fold improvement in the power-delay product of a simple comparator. Our scheme is ideally suited for comparators used in synchronous rectification. It is also broadly useful in applications where an asynchronous comparator is required, such as sensor interfaces, oscilloscope triggers, some types of analog-to-digital converters, and spiking-neuron circuits. The difference equations that govern our adaptive scheme may be represented by a unimodal discrete map. Therefore, near the limits of the scheme's stable regime of operation, we were able to experimentally confirm that there was a period-doubling route to chaos. Index Terms--Adaptive control, chaos, comparators, low power, predictive control.

Author(s): Richard H. R. Hahnloser (corresponding author) [1, 3]; Rahul Sarpeshkar [2, 4]; Misha A. Mahowald [1]; Rodney J. Douglas [1]; H. Sebastian Seung [2, 3] Digital circuits such as [...]

We present two algorithms for estimating the velocity of a visual stimulus and their implementations with analog circuits using CMOS VLSI technology. Both are instances of so-called token methods, where velocity is computed by identifying particular features in the image at different locations; in our algorithms, these features are abrupt temporal changes in image irradiance. Our circuits integrate photoreceptors and associated electronics for computing motion onto a single chip and unambiguously extract bidirectional velocity for stimuli of high and intermediate contrasts over considerable irradiance and velocity ranges. At low contrasts, the output signal for a given velocity tends to decrease gracefully with contrast, while direction-selectivity is maintained. The individual motion-sensing cells are compact and highly suitable for use in dense 1-D or 2-D imaging arrays. Index Terms - Analog CMOS, analog VLSI, machine vision, motion sensors, photoreceptors, smart vision chips, velocity sensors.

Sensitivity mismatch in complementary metal oxide semiconductor sense amplifiers commonly used in dynamic random access memory is studied. In the analysis, the sensitivity of the amplifier to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch and bitline load capacitance mismatch was obtained via a new derived expression. Simulations verified the formula's applicability.

We describe an FFT-based companding algorithm for preprocessing speech before recognition. The algorithm mimics tone-to-tone suppression and masking in the auditory system to improve automatic speech recognition performance in noise. Moreover, it is also very computationally efficient and suited to digital implementations due to its use of the FFT. In an automotive digits recognition task with the CU-Move database recorded in real environmental noise, the algorithm improves the relative word error by 12.5% at -5 dB signal-to-noise ratio (SNR) and by 6.2% across all SNRs (-5 dB SNR to +5 dB SNR). In the Aurora-2 database recorded with artificially added noise in several environments, the algorithm improves the relative word error rate in almost all situations.

A quasi-stable threshold voltage (V[sub t]) shift is imparted onto field-effect transistors (FETs) with organic semiconductors and polymer dielectrics. Adjustment of V[sub t] from accumulation mode to zero or depletion mode is demonstrated for both p-channel and n-channel FETs, and is accomplished by applying a depletion voltage to the gate prior to device operation. Hydrophobic dielectrics and dopant-resistant semiconductors were advantageous. A pixel circuit that utilizes this nonvolatile memory element is proposed. © 2002 American Institute of Physics. [ABSTRACT FROM AUTHOR]