Search

In this Paper, we have studied and compared the performance of two different configurations of simulation model advanced MOSFET devices which can be used for biosensor application. The bio-molecules like protein, biotin, streptavidin, APTES, etc., undergo label free electrical detection with the help of dielectrical modulation technique in order to overcome the limitations of short channel effect in a more efficient way. The bio-molecules trapped inside the cavity region change the electrical parameters of the MOSFET. Biosensors based on MOSFETs have certain issues, like short channel effects (SCEs) and problems related to scaling and power supply. Therefore the proposed device is better withstand to SCEs and can be consider as an alternative for biosensing applications. For channel material, silicon is used for both the configurations i.e. with stack and without stack model and we have also studied the performance of the device based on the analog as well as RF parameters by considering the protein as bio-molecule in the cavity. Two different oxide materials are used to design the device structure such as HfO2 (K = 25) and SiO2 (K = 3.9) and for simulation purpose the 2D Sentrausu TCAD simulator has been used. The sensing capability of this proposed dielectric modulated device can be applicable for IOT based applications. They can also be uses in health IOT systems for medical research applications and as bio chip sensor in wearable device so as to study the protein content of the human body.

In this paper a double gate MOSFET having non uniform channel doping with gate stack structure is explored to study the linearity analysis. The extractions of linearity parameters confirm the novelty of the device and also enable us to achieve better the analog/RF applications. This promising device has an advantage of showing higher cut-off frequency, reduced DIBL, better gate oxide reliability and limiting the effects of parasitic bipolar phenomenon. In this paper we have studied the detail analysis of important linearity parameters of this proposed device with respect to change in high K oxide thickness (toxh) to have clear ideas on different linearity parameters like VIP2, VIP3, IIP3 and IMD3 and their variations. The simulated results validate that the change in toxh of this device plays a significant role on improving the linearity performance and there by careful optimization of this parameters can infer achieving better and reliable analog/linearity performances for SOC applications.

In this work, we have made a relative assessment of lattice-matched In 0.17 Al 0.83 N/AlN/GaN normally off HEMT device with AlGaN back-barrier (BB) and without back-barrier by using device simulator. The utility of AlGaN BB on the said E-HEMT relaxes the channel, which reduces the short channel effects. It also reduces the total gate capacitance and simultaneously improves the cut- off frequency. The numerical modelings are done by the 2Dimenssional TCAD by means of HD mobility and matched with the previously accepted experimental result. Different device parameters are analyzed and compared with BB and without BB with the help of the numerical modeling. AlGaN back-barrier has further benefits in device parameters with comparison to without back-barrier i.e. less total gate capacitance and higher cut-off frequency. These outcomes prove the utility of proposed BB in such E-Mode GaN HEMTs can be a substitute way out in support of high power along with high-frequency purposes.

This paper illustrate the effect of gate material engineering on the performance of enhancement mode n ++ GaN/InAlN/AlN/GaN high electron mobility transistors (HEMTs). A comparative analysis of key device parameters is discussed for the Triple Material Gate (TMG), Dual Material Gate (DMG) and the Single Material Gate (SMG) structure HEMTs by considering the same device dimensions. The simulation results shows that an significant improvement is noticed in the key analysis parameters such as drain current (I d ), transconductance (g m ), cut off frequency (f T ), RF current gain, maximum cut off frequency (f max ) and RF power gain of the gate material engineered devices with respect to SMG normally off n ++ GaN/InAlN/AlN/GaN HEMTs. This improvement is due to the existence of the perceivable step in the surface potential along the channel which successfully screens the drain potential variation in the source side of the channel for the gate engineering devices. The analysis suggested that the proposed TMG and DMG engineered structure enhancement mode n ++ GaN/InAlN/AlN/GaN HEMTs can be considered as a potential device for future high speed, microwave and digital application.

In the present work, we have discussed the effect of InGaN back barrier on device performances of 100 nm gate length AlInN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) device and a wide comparison is made with respect to without considering the back barrier layer. The InGaN layer is introduced in the intension to raise the conduction band of GaN buffer with respect to GaN channel so that there is an improvement in the carrier confinement and at the same time witnessed excellent high frequency performance. The simulations are carried out using 2D Sentaurus TCAD simulator using Hydrodynamic mobility model by taking interface traps into consideration. Due to high value of two-dimensional electron gas (2DEG) density and mobility in AlInN/AlN/GaN MOS-HEMT device, higher drain current density is achieved. Simulation are carried out for different device parameters such as transfer characteristic (Id-Vg), transconductance factor (gm), drain induced barrier lowering (DIBL), Subthreshold slope (SS), conduction band energy, transconductance generation factor (gm/Id) and electric field. We have also examined the RF performance such as, total gate capacitance (Cgg), current gain cutoff frequency (fT) and power gain cutoff frequency (fmax) of the proposed devices. Use of InGaN back barrier tends to increase threshold voltage towards more positive value, reduced DIBL, and improves SS and significant growth in (gm/Id) by 5.5%. It also helps to achieve better frequency response like substantial increase in fT up to 91 GHz with current gain 60 dB as compare to 67 GHz with 56 dB for the device without considering back barrier and increase in fmax up to 112 GHz with respect 94 GHz. These results evident that use of InGaN back barrier in such devices can be better solution for future analog and RF applications.

This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different spacer variations with an aim to analysis the effects of short channel and various performance metrics. In this work we have taken silicon as the channel material with non-uniform doping for studying the analog and RF performances. Spacer's materials having different permittivities were used to understand their effect on the device performance. Based on the simulations, we can conclude that analog and Radio Frequency performance of the device shows an significant improvement with addition of spacer layer. We have used computer aided design (TCAD) simulations by SILVACO International.

This work demonstrates a comparative analysis of various types of Double-Gate MOSFET, aims at enhancing the analog, linearity performances and these devices are more protective to short-channel effects (SECs). We have studied the linearity performance of DG-MOSFET by considering channel material as InAs and simultaneously incorporating gate stack technique. Variations oxide materials by considering channel as InAs and finally their comparison were thoroughly studied to have a better understanding of different linearity parameters. Various Figure-of-merits(FOMs) such as trans-conductance factor, VIP2, VIP3, IIP3 are thoroughly analysed for various high-K oxide materials along with gate stack technology. From the simulation results it is found that the performances of the device changes with respect to change in different oxide materials and it is also inferred that gate stack technology has also significant effect in the linearity performances. In this work, we have used the (TCAD) simulations by 2D ATLAS, Silvaco International to carry out the simulations.

In the proposed work, the study and thorough analysis of JLTMCSG MOSFET has been done. Its comparison with JLDMCSG MOSFET also being done based on different parameter variations like linearity study taking into account various suitable linearity metrics such as gm1, gm2, gm3,1-dB compression point, VIP2, VIP3 and IIP3. The analysis suggests that if designed properly JLTMCSG MOSFET will have superior linearity performance. At the same time distortion can be reduced due to lowered drain induced barrier lowering. It has a higher and more uniformity produced in the electric field which is suitable applications in microwave applications and RF communication and low noise amplifiers.

In the present work, we propose and perform extensive simulation study of the novel device structure having a p-GaN back barrier layer inserted in the conventional AlInN/AlN/GaN Gate-Recessed Enhancement-Mode HEMT device for reducing the short channel effects, gate leakage and enhancing the frequency performance. The influence of the p-GaN back barrier layer on the device performance of the newly proposed structure is done using 2D Sentaurus TCAD simulations. The simulations use Drift–Diffusion (DD) model, Masetti and Canali model, which are calibrated/validated with the previously published experimental results. Simulation are done to analyze the transfer characteristics, transconductance (gm), Gate leakage current (Ig), drain induced barrier lowering (DIBL), subthreshold slope (SS), threshold voltage (Vth), On-current Off-current ratio (Ion/Ioff), gate capacitance (Cgg) and cut off frequency (fT) of the proposed device. A comparison is done between the device without back barrier layer and the proposed device with p-GaN back barrier layer. Use of p-GaN back barrier layer helps to achieve a higher positive Vth due to the depletion effect, reduced Ig, reduced DIBL, prevents degradation of SS and helps to increase the fT. Very impressive fT up to 123 GHz, as compared to 70 GHz for the device without back barrier. These results indicate that AlInN/AlN/GaN Gate-Recessed Enhancement-Mode HEMT structure with p-GaN back barrier is a promising candidate for microwave and switching application.

In the present paper, we propose a novel device structure by introducing a source field-plated AlGaN/GaN in the metal oxide Semiconductor high electron mobility transistors (MOS-HEMT) structure having a relatively short gate length and short gate-to-drain distances. The 2D breakdown analysis is performed using Sentaurus TCAD simulator. The effects of gate to drain distance ( L g d ), source field plate length ( L f p ) and passivation layer thickness ( t p ) on breakdown voltage (BV) is analyzed. The simulations are done using the drift–diffusion (DD) model, which is calibrated/validated with the previously published experimental results. The breakdown voltage is observed to increase with increase in L f p and t p . Very high breakdown voltage of 752.8 V is obtained by optimizing the L f p to 3 µm and t p to 200 nm at a fixed gate to drain distance of 3.4 µm. The results show a great potential application of the ultra-thin HfAlO source field plated AlGaN/GaN MOS-HEMT to deliver high currents and power densities in high power microwave technologies.

This work systematically investigated the effect of high-[Formula: see text] oxide materials on the performance of InAlN/GaN heterostructure underlap double gate (DG) MOS-HEMTs by considering 2D Sentaurus TCAD simulation. During the course of simulation, hydrodynamic mobility model was implemented and the obtained results were used for validating the model with the previously published experimental results. Different device performance parameters are thoroughly studied for different high-[Formula: see text] oxide materials by performing extensive simulations. It is verified that short channel effects (SCEs), key analog and RF figures of merits parameters and [Formula: see text]th improved with an increase in the value of high-[Formula: see text] oxide material. Moreover, it is also revealed that there is a significant growth in the values of key analog and RF figures of merits with respect to high-[Formula: see text] values. This analysis suggested that use of a suitable value of high-[Formula: see text]-valued oxide material in InAlN/GaN heterostructure underlap DG MOS-HEMTs can be one of the alternatives for future high speed and microwave applications.

In this paper we study the analog performance and also extract the RF parameters of Graded channel Gate stack (GCGS) DG MOSFET structure for different high K materials. A relative assessment was also carried out by using 2D Sentrausu TCAD simulator for different high-K oxide layers. This novel device can be one of the promising alternatives to the existing devices for future high speed switching and low power circuit applications. It has several advantages such as reducing leakage current, getting higher breakdown voltage, reduced bipolar parasitic effects and improved frequency response. The given device must be investigated with respect to different doping profile and high K materials to have better reliability. Non-quasi-static (NQS) effect was also considered to extract the RF parameters for a given graded doping profile across the channel for different high-K materials. The result evident that variation of high K oxide materials with respect to high-low doping profile across the channel gives useful information's on the analog and RF performance of the proposed device.

In this paper we have made a relative assessment of Graded channel Gate stack (GCGS) DG MOSFET structure for different high K materials by interchanging forward and reverse doping profile across the channel by using 2D Sentrausu TCAD simulator. This structure consist of gate stack (GS) engineering (high K), and non-uniformly channel engineering (GC) to overcome the short channel effects and improving the device performance. This novel device can be a substitute to the current devices for future high speed switching and low power circuit applications. It has the benefits of reducing leakage current, better breakdown voltage, reduced bipolar parasitic effects and improved frequency response. The given device must be explored with respect to different doping profile and high K materials to have better reliability and dependency before fabrication. Different analog and Rf performance parameters of the proposed device was studied with respect to different high K materials for better understanding and future application. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure along with proper validation. The result indicates that the variation of doping profile and high K oxide materials have significant effects on the performance of the said device.

We have demonstrated the impact of dual material gate (DMG) and triple material gate (TMG) on the performance of enhancement mode n++GaN/InAlN/AlN/GaN high electron mobility transistors (HEMTs) and a comparison is made with the performance of single material gate (SMG) enhancement mode n++GaN/InAlN/AlN/GaN high electron mobility transistors (HEMTs) by using two-dimensional Sentaurus TCAD device simulation. Thermodynamic transport model is used for simulating the proposed device. We have systematically investigated the advantage of DMG and TMG over SMG device. The key idea in this paper is to reveal the enhancement in drain current (I d ), transconductance, cut off frequency and RF current gain of DMG and TMG device over SMG normally off n++GaN/InAlN/AlN/GaN high electron mobility transistors. The result shows that the DMG and TMG enhancement mode n++GaN/InAlN/AlN/GaN high electron mobility transistors is potentially better candidate for future high speed, microwave and digital application.

In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed device due to variation of barrier layer thickness from 2 nm to 6 nm. Various parameters such as transconductance ([Formula: see text], second-order transconductance ([Formula: see text]), third-order transconductance ([Formula: see text]), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3) and third-order intermodulation distortion (IMD3) of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) are discussed. The simulated results obtained confirms that by careful optimization of barrier layer thickness linearity characteristics of this proposed device can be improved, which can be suitable for analog and circuit applications.

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.