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Cu–Cu bonding is a key process in fine pitch Cu interconnect in 3-dimenssional Si integration. Despite the excellent electrical property and pattern ability of Cu material, the Cu–Cu bonding process is affected by the high bonding temperature and easy oxidation. Thus, the ability to protect the copper surface in a reactive air environment is very important in Cu–Cu bonding, especially for die–to–wafer Cu bonding applications. We studied Cu–Cu bonding using a copper nitride nanolayer as an antioxidant passivation layer and investigated the stability of the copper nitride nanolayer over 7 days and its decomposition capability across temperatures of up to 400 °C. We found that the copper nitride (Cu4N) nanolayer formed by two-step Ar/N2 plasma treatment protected the copper surface from further oxidation in the air, and that the energy required for thermal decomposition of the copper nitride nanolayer in this study was about 29.6 kJ/mol. It can be seen that the bonding temperature of Cu–Cu bonding can be sufficiently lowered by using a low–temperature decomposition property of copper nitride.

Low-temperature solderless Cu–Cu bonding is an important technology for advanced packaging, such as fine-pitch 3-D packaging and heterogeneous integration. In this study, we prepared an oxidation-free Cu surface using an optimized N2 plasma process in a two-step Ar/N2 plasma treatment based on the design of the experiment method, to improve direct Cu–Cu bonding quality at 260 °C. The N2 plasma treatment process was optimized using the Minitab optimizer with chemical state results obtained by X-ray photoelectron spectroscopy (XPS) analysis. The Cu surface treated under the two-step Ar/N2 plasma with optimized N2 plasma conditions not only formed Cu nitride well, but the surface remained without further oxidation for at least one week at room temperature. The Cu–Cu bonding was performed at the low bonding temperature of 260 °C and low bonding pressure of 0.9 MPa for 1 hour, and the bonded interface was evaluated using scanning acoustic tomography (SAT) and field emission scanning electron microscope (FE-SEM) images. We measured shear strength to estimate the bonding interface quality of the oxidation-free Cu–Cu bonding specimen. A maximum shear strength of 62.6 MPa was obtained. Our bonding results demonstrated remarkably improved Cu–Cu bonding quality compared with other previous Cu–Cu joint studies that used Sn, Cu/Ag nanoparticles, or Cu composites.

An anti-oxidant Cu layer was achieved by remote mode N2 plasma. Remote mode plasma treatment offers the advantages of having no defect formation, such as pinholes, by energetic ions. In this study, an activated Cu surface by Ar plasma chemically reacted with N free radicals to evenly form Cu nitride passivation over the entire Cu surface. According to chemical state analysis using XPS, Cu oxidation was effectively prevented in air, and the thickness of the Cu nitride passivation was within 3 nm. Based on statistical analysis using the DOE technique with N2 plasma variables, namely, RF power, working pressure, and plasma treatment time, we experimentally demonstrated that a lower RF power is the most effective for forming uniform Cu nitride passivation because of a lower plasma density. When the N2 plasma density reached approximately 109 cm−3 in which the remote mode was generated, high energy electrons in the plasma were significantly reduced and the amount of oxygen detected on the Cu surface was minimized. Finally, low temperature (300 °C) Cu–Cu bonding was performed with a pair of the anti-oxidant Cu layers formed by the remote mode N2 plasma. Cu atomic diffusion with new grains was observed across the bonded interface indicating significantly improved bonding quality over bare Cu–Cu bonding.

The success of wafer-to-wafer or chip-to-chip bonding in 3-D packaging relies on the development of planarized, activated, and oxygen-free Cu surface. Preventing Cu oxidation is becoming a crucial issue in chip-to-chip bonding processes. In this study, a two-step plasma pretreatment process was demonstrated to prevent copper oxidation by virtue of forming a nitride passivation layer on the Cu surface. The two-step plasma pretreatment consisted of Ar plasma to activate the Cu surface, followed by N2 plasma to passivate the Cu surface. It was found that the pressure in the Ar plasma step had the greatest effect on the formation of nitrate passivation on the Cu surface, and the lower the pressure in the Ar plasma step, the better the formation of copper nitrate in the N2 plasma step. The two-step plasma pretreatment provided a nitride-passivated Cu surface and significantly improved the Cu-to-Cu bonding quality. This process may enable Cu-to-Cu bonding in an atmospheric environment.

Low-temperature Cu-Cu bonding technology plays a key role in high-density and high-performance 3D interconnects. Despite the advantages of good electrical and thermal conductivity and the potential for fine pitch patterns, Cu bonding is vulnerable to oxidation and the high temperature of the bonding process. In this study, chip-level Cu bonding using an Ag nanofilm at 150 °C and 180 °C was studied in air, and the effect of the Ag nanofilm was investigated. A 15-nm Ag nanofilm prevented Cu oxidation prior to the Cu bonding process in air. In the bonding process, Cu diffused rapidly to the bonding interface and pure Cu-Cu bonding occurred. However, some Ag was observed at the bonding interface due to the short bonding time of 30 min in the absence of annealing. The shear strength of the Cu/Ag-Ag/Cu bonding interface was measured to be about 23.27 MPa, with some Ag remaining at the interface. This study demonstrated the good bonding quality of Cu bonding using an Ag nanofilm at 150 °C.

3D packaging is able to keep the scaling in semiconductor market. Increased and shorter interconnects achieved by vertical stacking have benefits such as improved performance, reduced signal delay, and small form factor. In order to obtain high-quality 3D packaging applications, the integration of heterogeneous devices through bonding technologies is very important. Low temperature and pressure are essential during the bonding process because most of logic/memory devices has many metal and low-k dielectric layers, which are vulnerable to thermal budget and mechanical stress. Therefore, a small amount of solder with a low melting point is presently used on the top of the copper pillar for mass production. But, solder creates an intermetallic compound with copper at the bonding interface and cannot be applied to fine pitch patterns due to their reflow characteristics. Thus, Cu is emerged as a promising interconnect, but Cu-Cu bonding has few challenges because copper is easily oxidized and has a high melting point. In this paper, copper nitride, which prevents oxidation of the copper surface and promotes low temperature bonding, was studied by two step Ar/N 2 plasma treatment. The optimum thickness of copper nitride passivation was derived using the design of experiment. It was also found that the copper nitride layer was almost decomposed at a temperature of 200°C.

The introduction of an organic–inorganic dielectric material into the redistribution layers in fan-out wafer level packaging technology has been investigated to improve mechanical stress, thermal stability, and electrical breakdown compared to organic dielectric materials. A photo-definable organic–inorganic dielectric material called polysilsesquioxane (PSSQ) has been studied in this work. The photo-definable PSSQ dielectric allows a simultaneous UV patterning and curing process. A PSSQ sample was prepared by spin-coating on a 6-in. Si wafer, pre-baking at 100 °C for 5 min, UV exposure, and then PGMA developing. The cured PSSQ films have a dielectric constant from 2.0 to 2.38 and dielectric loss from 0.0001 to 0.005. In addition, the 2 μm line patterns were obtained after 10 min of UV exposure. It has been demonstrated that PSSQ dielectric materials can provide excellent process capability of simultaneous UV patterning and curing process.

Cu-to-Cu bonding is necessary for high density, fine-pitch interconnect and high bandwidth in 3D stacking technology. Although various Cu-to-Cu bonding studies have been reported so far, few challenges still are remaining such as atmospheric oxidation of Cu, high bonding temperature and pressure not suitable for mass production. In this study, we evaluated low temperature Cu-to-Cu bonding with two step plasma treatment using Ar and N2. The effects of Ar and N2 plasma treatment on Cu and SiO2 surfaces were investigated especially for Cu/SiO2 hybrid bonding applications. The two-step plasma treatment was produced copper nitride passivation layer to prevent further oxidation of copper in the air. The two-step plasma treated SiO2 surface showed some nitrogen bonding with Si, but no effects on electrical property.

As an interconnect scaling in planar (2D) chips face a technical bottleneck, the vertically stacked structure called 3D integrated circuit (IC) packaging becomes a major packaging technology for the next generation heterogeneous integration. 3D IC packaging technology provides reduced interconnect lengths between the chips and improves electrical signal and power delivery problems. Among three core unit processes in 3D packaging, a wafer bonding process is still an immature process for mass production compared to through Si via formation and Si thinning. Most bonding materials used in stacked ICs so far are solder materials or Cu pillars with Sn cap, however with the demand of fine pitch less than 10um in a bonding layer, Cu bonding is of great interest in 3D IC heterogeneous packaging. Despite the excellent electrical and mechanical properties and fine pitch patternability, Cu bonding process has several challenges to be resolved, such as easy oxidation, high bonding temperature, extremely low dishing planarization and so on. In this study, the two-step plasma treatment method using Ar and N 2 was applied on the copper surface to achieve low temperature Cu bonding. N 2 plasma process of two-step plasma treatment was optimized by RSM (response surface methodology) based on CCD (central composite design) in DOE (design of experiment) system. With the optimized plasma treatment, the Cu bonding quality has been significantly improved compared to Cu bonding without any surface treatment at 300°C. Also, it has been demonstrated that the copper nitride passivation layer prevents further oxidation up to 1 week in air.

Wafer stacking technology provides reduced interconnect delay, improved bandwidth, reduced form factor, and decreased cost. Solder-based metallic die bonding is presently utilized in high-volume manufacturing, but Cu-based metallic wafer bonding is quickly becoming a key bonding technique for next generation 3D IC and heterogeneous stacking applications. In this study, Ar–N2 plasma treatment on Cu surface was investigated to passivate Cu surface with nitrogen and to enhance the bonding quality of Cu-to-Cu wafer bonding. The Ar–N2 plasma treatment was performed by conventional DC sputtering under 5 mTorr working pressure with different Ar–N2 partial pressures. Then, the effect of Ar–N2 plasma treatment on Cu surface was evaluated structurally and electrically. It was observed that the Ar–N2 plasma treatment with high nitrogen partial pressure over a sufficient plasma treatment time provided activated Cu surface, reduction of copper oxide and chemisorbed nitrogen, and copper nitride passivation. The Ar–N2 plasma treatment of Cu surface was found to be a potential pretreatment method for Cu-to-Cu bonding.

SnO x thin films are potentially excellent conductive material with large hole mobility and have attracted ever-increasing attention for next generation electronic applications. In this study, SnO x thin films were deposited on a borosilicate glass substrate by radio frequency (rf) reactive sputtering using a SnO/Sn (9:1 mol% ratio) composite target. The composite target was used to produce a chemically stable composition of SnO x thin film while controlling structural defects by chemical reaction between tin and oxygen. The effects of oxygen contents and annealing on various properties of SnO x thin films were studied. The structural analysis was carried out using X-ray photoelectron spectroscopy and X-ray diffraction. The electrical and optical analyses were performed by the Van der Pauw Hall effect measurement and UV/VIS spectrometer, respectively. SnO x thin films at P O2 = 0% (annealed) and 3% (as deposited) exhibited a p-type conductivity of 0.09–0.11 Ω − 1 cm − 1 , a hole mobility of 0.2–1.2 cm 2 V − 1 s − 1 , and a hole concentration of ~ 10 18 cm − 3 . Also, these thin films showed the transmittance of about 70% and an optical bandgap of 2.75–3.01 eV.

This study depicts the comparative research between sputtered and electroplated Cu surfaces using argon and nitrogen ion bombardments to form copper nitride passivation layers. The thin copper nitride layer is formed in order to prohibit Cu oxidation on copper surface and to lower bonding temperature in Cu-Cu thermo-compression bonding process. Argon ion bombardment was applied to activate and clean copper surface. Nitrogen ion bombardment was utilized to passivate the Cu surface after argon ion bombardment. The sputtered Cu surface tended to form Cu 4 N layer, while the electroplated Cu surface tended to form Cu 3 N layer. In comparison with electroplated Cu, the sputtered Cu had a lower roughness and a slightly higher sheet resistance. The bonding quality of the sputtered Cu samples was better than that of the electroplated samples. Further research should improve the roughness and copper nitride properties of the Cu surface.

Copper nitride passivated surface has been characterized and optimized by the design of experiment (DOE) technique with the aim of low-temperature (300°C) Cu-Cu bonding. In order to generate an oxidation-free surface prior to Cu-Cu bonding process, N 2 plasma treatment was performed on Cu surface followed by Cu surface activation and cleaning by Ar plasma in the same conventional DC sputter chamber. In this study, N 2 plasma treatment conditions were optimized using the response surface methodology (RSM) based on central composite design (CCD) in DOE. The chemical states of nitride passivated Cu surface were analyzed by XPS profiles and then, several meaningful peak areas of each element were calculated by a deconvolution technique. These peak areas and surface roughness by AFM were used as the input values for the response optimization process. Cu-Cu bonded interface quality using optimized plasma conditions at low-temperature (300°C) has been significantly improved and it shows this research has great potential for Cu-Cu bonding in mass production.

The technology trends of next generation electronic packaging are moving toward heterogeneous 3D packaging systems. One of the key processes of 3D packaging system is Cu-to-Cu bonding, which is highly dependent on the planarized, activated, and oxygen-free Cu surface. A two-step plasma treatment is studied to form a Cu surface that does not react with oxygen and improves the Cu bonding interface quality at low bonding temperature (300 °C). In this study, the effects of two-step plasma treatment on both sputtered and electroplated Cu surfaces were evaluated through structural, chemical, and electrical analysis. The Cu bonding interface was studied by scanning acoustic tomography analysis after the thermocompression bonding process. Both sputtered and electroplated Cu thin films had the preferred orientation of (111) plane, but sputtered Cu exhibited larger grains than the electroplated Cu. As a result, the roughness of sputtered Cu was lower, and the resistivity was higher than that of electroplated Cu. Based on X-ray photoelectron spectroscopy analysis, the sputtered Cu formed more copper nitrides and fewer copper oxides than the electroplated Cu. A significant improvement in bonding quality at the Cu bonded interface was observed in sputtered Cu.

For low temperature Cu-to-Cu bonding process, copper nitride passivation on Cu surface was studied via two-step plasma treatments using argon and nitrogen gases. The two-step plasma treatment of copper nitride passivation was processed in a DC sputtering vacuum chamber. Cu surface was activated with Ar ion bombardment in Ar plasma and immediately followed by N 2 plasma treatment for surface passivation. In this study, various parameters of Ar plasma such as RF power, working pressure and treatment time were controlled to find an optimal Cu surface where nitride passivation was formed. The degree of nitridation and oxidation after the plasma treatments was characterized quantitatively using XPS analysis. Lastly Cu-to-Cu bonding was performed at 300°C and the effect of copper nitride passivation on Cu bonding quality was evaluated by SAT and SEM analysis.

The development of 3D integration has caused a major technology paradigm shift to all integrated circuit (IC) devices, interconnects, and packages. Despite the benefits of 3D integration, this process faces the key challenge of thermal management, especially for high power and high density IC devices. Due to the limitations of conventional thermal solutions, liquid cooling technology has become a field of great interest for IC thermal management. In this study, an on-chip liquid cooling module with three different through Si vias (TSVs) and a fixed microchannel structure has been fabricated on an Si wafer using deep reactive ion etching and anodic bonding, followed by a grinding and dicing process. Pressure drop, coolant flow, and temperature difference before and after liquid flow were experimentally measured. TSV depth and diameter have been shown to have little effect on the change of pressure drop; however, shallower TSV depth and larger TSV diameter led to improved liquid cooling performance. The trapezoidal TSV showed slightly more effective cooling than did the scalloped TSV or the straight TSV.

Thermal management in 3D IC is an important factor in terms of IC performance and reliability. In this study, the feasibility of Cu TSV as a heat dissipation path was experimentally investigated. Si wafers with or without Cu TSV were point-heated at various temperatures and thermal diffusion in the specimens was observed using IR microscope. Si wafers with Cu TSV showed higher top surface temperature than ones without Cu TSV as the heating power increased. This phenomenon was attributed to the preferred heat transfer through Cu TSV in the vertical direction due to high thermal conductivity of Cu. This implies that Cu TSV is an effective vertical heat dissipation path. Display Omitted The feasibility of Cu TSV as a heat dissipation path was experimentally investigated.Thermal diffusion of point-heated Si wafer through Cu TSV was observed using IR microscope.Due to high thermal conductivity of Cu, heat was preferentially transferred vertically through Cu TSV.This implies that Cu TSV is an effective vertical heat dissipation path.

As the IC devices are rapidly scaled down, IC integration has faced several technical bottlenecks: further miniaturization, power delivery and distribution, signal/power integrity, and heat dissipation. In this regard, chip or wafer stacking processes have attracted attention to improve an interconnect delay and an inter-die bandwidth, reduce a form factor, and decrease manufacturing costs. Vertically stacking technology not only enhances device performance, but also can realize heterogeneous packaging systems for the next generation heterogeneous integration. Of the three unit processes in the vertical stacking system, Cu-to-Cu bonding has emerged as a core technology for efficient power density, high bandwidth, and fine-pitch connecton. Various Cu-to-Cu bonding studies have been reported, such as thin metal passivation on Cu surface, self-assembled monolayer that passivates Cu surface with alkane-thiol, surface activated bonding that removes surface oxide layers and contaminants by plasma treatment, and direct bonding interconnect that enables Cu/SiO2 hybrid bonding. Despite many studies, Cu surface oxidation and high bonding temperature are still major issues to be resolved in high volume manufacturing. Sustainable, oxidization-free copper surface prior to Cu-to-Cu bonding is critical, especially since chip-to-chip bonding must still be performed in the air. Therefore, in this study, the copper surface passivation using the two-step plasma treatment has been investigated. The Cu-to-Cu bonding process of less than 300℃ was investigated using the copper nitride passivation. The copper nitride passivation layer was formed on 8-inch Si/SiO2/50nm Ti/1μm Cu using the two-step Ar-N2 plasma treatment process. The purpose of two step plasma treatment is first to remove copper oxides and any contaminants through Ar plasma, activate the Cu surface, and then form a copper nitride layer through N2 plasma. This metastable passivation of couple nanometer thickness prevents further oxidation and reduces surface roughness. In addition, since a copper nitride tends to decompose at 300oC or lower it does not adversely affect Cu bonding interface. The two-step plasma treatment was optimized to improve Cu bonding quality, and optimization was systematically carried out by the response surface methodology (RSM) based on a central composite design (CCD) in design of experiment (DOE). It has been found that copper nitride passivation lasts at lasts for 1 week.. The two-step plasma treatment showed the Cu2O removal and Cu4N formation on the Cu surface. Under the optimized two step Ar-N2 plasma treatment at 300℃, Cu-to-Cu bonding quality has significantly improved compared to the Cu-to-Cu bonding without any surface treatment. The interfacial strength measured by 4-point bending test and shear test and electrical measurements will be discussed.

The surface planarity of polymeric interlayer dielectrics becomes a key factor for the multi-level interconnection for fan-out wafer level package. The surface topography of polymeric interlayer dielectrics depends on the underlying metal patterns, and the higher degree of planarization was observed with narrower line and larger space. The pressing method is proposed to flatten the surface undulations. The surface of PBO was pressed with a pressing plate during the soft-bake process, and the surface planarity was observed to be improved effectively.

3D packaging technology offers great benefits such as reduced power consumption, improved performance, and reduced form factor. Among three key processes in 3D packaging a low temperature Cu-to-Cu wafer bonding is the subject of interest in this study. To accommodate high conductivity, non-formation of intermetallic compound, fine pitch connectivity, high pin count, and low cost, Cu-to-Cu wafer bonding is becoming increasingly important in advanced IC device packaging manufacturing. However, for high bonding quality, Cu-to-Cu wafer bonding requires high temperature process above $400^{\circ}\mathrm{C}$, which is not allowed in IC device packaging manufacturing. In this study the effect of Ar-N 2 plasma treatment on Cu surface was investigated for low temperature Cu-to-Cu wafer bonding applications. Ar gas is used in a plasma ignition and the activation of Cu surface by ion bombardments, and the purpose of N 2 gas was to passivate u surface from contaminations such as –O or –OH. The Cu/Ti/SiO 2 /Si specimens were fabricated on 8-inch Si wafers. Then various Ar-N 2 plasma treatments were performed on Cu wafer surface. After the Ar-N 2 plasma treatments, electrical and structural properties were analyzed by X-ray diffraction, X-ray photoelectron spectroscopy, atomic force microscope, and 4-point probe measurements. It has been confirmed that Ar-N 2 plasma treatment can provide copper oxide removal and copper nitride passivation at the topmost Cu surface.

Department of Mechanical System Design Engineering, Seoul National University of Science and Technology, 232 Gongneung-ro Nowon-gu, Seoul 139-743, Korea(Received October 19, 2015: Corrected December 23, 2015: Accepted December 24, 2015)초록: 전자소자의 다기능, 고밀도, 고성능, 그리고 소형화는 전자 패키지 기술에 초미세 피치 플립 칩, 3D 패키지,유연 패키지, 등 새로운 기술 패러다임 전환을 가져왔으며, 이로 인해 패키지 된 칩의 열 관리는 소자의 성능을 좌우하는중요한 요소로 대두되고 있다. Heat sink, heat spreader, TIM, 열전 냉각기, 등 많은 소자 냉각 방법들 중 본 연구에서는냉매를 이용한 on-chip 액체 냉각 모듈을 Si 웨이퍼에 제작하고, 마이크로 채널 디자인에 따른 냉각 효과를 분석하였다.마이크로 채널은 딥 반응성 이온 에칭을 이용하여 형성하였고, 3 종류 디자인(straight MC, serpentine MC, zigzag MC)으로 제작하여 마이크로 채널 디자인이 o냉각 효율에 미치는 영향을 관찰하였다. 가열온도 200C, 냉매 유동속도 150 ml/min의 o경우에서 straight MC가 약 44C의 높은 냉각 전후의 온도 차를 보였다. 냉매의 흐름과 상 변화는 형광현미경으로관찰하였으며, 냉각 전후의 온도 차는 적외선현미경을 이용하여 분석하였다.Abstract: The demand for multi-functionality, high density, high performance, and miniaturization of IC devices hascaused the technology paradigm shift for electronic packaging. So, thermal management of new packaged chips becomesa bottleneck for the performance of next generation devices. Among various thermal solutions such as heat sink, heatspreader, TIM, thermoelectric cooler, etc. on-chip liquid cooling module was investigated in this study. Micro-channelwas fabricated on Si wafer using a deep reactive ion etching, and 3 different micro-channel designs (straight MC,serpentine MC, zigzag MC) were formed to evalute the effectiveness of liquid cooling. At the heating temperature of200

Display Omitted Wafer level bonding and stacking process for 3D stacked IC was proposed and evaluated.Cu bumps surrounded by recessed SiO2 were thermo-compression bonded and evaluated.Bonding defects like voids caused deviation of interfacial electrical resistance.Wafer alignment was affected by uneven bumps, the bonding fixture and wafer warpage.The overall wafer warpage showed maximum bow height of 100µm at bonding step. Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step.

3D integration enhances RC delay mitigation, improves inter-die bandwidth, and has routing advantages for the next generation integrated circuit technology. To realize the advantages of 3D integration, metallic bonding between different dies or wafers is necessary. So, Cu-to-Cu metallic bonding is, without doubt, a key process needed for 3D integration. In this study, Ar plasma treatment on the Cu surface for Cu thermo-compression bonding temperature less than 400 °C was investigated. Ar plasma treatment on the Cu thin film was performed using a conventional DC sputtering technique. The effect of Cu surface modified by Ar plasma was studied for Cu-to-Cu bonding. Also, the influence of Ar plasma treatment on the Cu surface was evaluated structurally and electrically.

Seoul National University of Science and Technology, 232 Gongneung-ro, Nowon-gu, Seoul 139-743, Korea(2014년 8월 7일 접수: 2014년 9월 5일 수정: 2014년 9월 16일 게재확정 )Abstract: The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in powerconsumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solderstructure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumplessinterconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompressiontechnology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirementsfor Cu bumpless technology are the planarization, contamination-free surface, and surface activation. Keywords: Bumpless, Interconnect, Fine-pitch, Cu bonding

Dept. of Mechanical System Design Eng., Seoul National University of Science and Technology, 232 Gongreung-ro, Nowon-gu, Seoul 139-743, Korea(2014년 9월 19일 접수: 2014년 9월 25일 수정: 2014년 9월 29일 게재확정 )초록:본 연구에서는 3차원 적층 집적회로 구조에서 Cu TSV를 활용한 열관리 가능성에 대해 살펴보았다. Cu TSV가 있는 실리콘 웨이퍼와 일반 실리콘 웨이퍼 후면부를 점열원을 이용하여 가열한 후 전면부의 온도 변화를 적외선 현미경을 이용하여 관찰하였다. 일반 실리콘 웨이퍼의 경우 두께가 얇아지면서 국부적인 고온영역이 관찰됨으로서 적층 구조에서 층간 열문제의 가능성을 확인할 수 있었다. TSV 웨이퍼의 경우 일반 실리콘 웨이퍼보다 넓은 영역의 고온 분포를나타내었으며, 이는 Cu TSV를 통한 우선적인 열전달로 인한 것으로 적층 구조에서 Cu TSV를 이용한 효과적인 열관리의 가능성을 나타낸다.Abstract: In this study, we investigated the effects of Cu TSV on the thermal management of 3D stacked IC.Combination of backside point-heating and IR microscopic measurement of the front-side temperature showed evolutionof hot spots in thin Si wafers, implying 3D stacked IC is vulnerable to thermal interference between stacked layers. CuTSV was found to be an effective heat path, resulting in larger high temperature area in TSV wafer than bare Si wafer,and could be used as an efficient thermal via in the thermal management of 3D stacked IC. Keywords: thermal via, 3D stacked IC, Cu TSV, thermal management

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8 Ω m. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.