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For the development of reliable vertical GaN transistors, a detailed analysis of the robustness of the gate stack is necessary, as a function of the process parameters and material properties. To this aim, we report a detailed analysis of breakdown performance of planar GaN-on-Si MOS capacitors. The analysis is carried out on capacitors processed on different GaN bulk doping (6E18 Si/cc, 6E17 Si/cc and 2.5E18 Mg/cc, p-type), different structures (planar, trench-like) and different geometries (area, perimeter and shape). We demonstrate that (i) capacitors on p-GaN have better breakdown performance; (ii) the presence of a trench structure significantly reduces breakdown capabilities; (iii) breakdown voltage is dependent on area, with a decreasing robustness for increasing dimensions; (iv) breakdown voltage is independent of shape (rectangular, circular). TCAD simulations, in agreement with the measurements, illustrate the electric field distribution near breakdown and clarify the results obtained experimentally., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][Research for GaN technologies, devices, packages and applications to address the challenges of the future GaN roadmap][UltimateGaN][826392]

Developing high quality GaN/dielectric interfaces is a fundamental step for manufacturing GaN vertical power transistors. In this paper, we quantitatively investigate the effect of planar etching treatment and trench formation on the performance of GaN-based MOS (metal oxide semiconductor) stacks. The results demonstrate that (i) blanket etching the GaN surface does not degrade the robustness of the deposited dielectric layer; (ii) the addition of the trench etch, while improving reproducibility, results in a decrease of breakdown performance compared to the planar structures. (iii) for the trench structures, the voltage for a 10 years lifetime is still above 20 V, indicating a good robustness. (iv) To review the trapping performance across the metal-dielectric-GaN stack, forward-reverse capacitance-voltage measurements with and without stress and photo-assistance are performed. Overall, as-grown planar capacitors devoid of prior etching steps show lowest trapping, while trench capacitors have higher interface trapping, and bulk trapping comparable to the blanket etched capacitors. (v) The nanostructure of the GaN/dielectric interface was characterized by high resolution scanning transmission electron microscopy (HR-STEM). An increased roughness of 2-3 monolayers at the GaN surface was observed after blanket etching, which was correlated to the higher density of interface traps. The results presented in this paper give fundamental insight on how the etch and trench processing affects the trapping and robustness of trench-gate GaN-MOSFETs, and provide guidance for the optimization of device performance., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][ECSEL Joint Undertaking (JU)][Grant Agreement No. 826392][UltimateGaN]

This paper investigates the kinetics of buffer trapping in GaN-based normally-off high-voltage transistors. The analysis was carried out on transfer-length method (TLM) structures. By means of a custom setup, (i) we investigated the trapping and de-trapping processes induced by a large vertical bias and identified different mechanisms, responsible for the storage of negative and positive charge in the buffer. (ii) temperature-dependent analysis was carried out to evaluate the time constants associated to negative and positive charge build-up. Remarkably, the results indicate that the activation energy for negative charge trapping is ~0.3 eV, which is much lower than the ionization energy of carbon acceptors (0.8-0.9 eV). This result is explained by considering that trapping and de-trapping are not dominated by thermal processes (thermal emission from acceptors), but by transport mechanisms, that limit the transfer of charge to trap states. (iii) in the recovery experiments, after low stress bias negative charge trapping dominates. After high stress bias, also the effect of positive charge generation is detected, and the related activation energy is evaluated. The results presented within this paper clearly indicate that the trapping and de-trapping kinetics of normally-off GaN HEMTs are the results of the interplay of transport-limited conduction processes, that result in a low thermal activation (Ea~0.3 eV), compared to that of CN acceptors., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][ECSEL Joint Undertaking (JU)][UltimateGaN][grant agreement No 826392]

The degradation mechanisms of AlGaN/GaN HEMTs adopting Fe and C co-doping, with high and low carbon doping concentration were investigated by means of hot-electron step stress and 24 hours stress tests. Firstly, DC and EL characterization at room temperature are summarized, then the parametric evolution during hot-electron step stress tests at the semi-on state was compared, the assumption for the degradation mechanism is that hot-electrons activated the pre-existing traps in the buffer, attenuate the electric field in the gate drain access region and damaging the gate contact, the parametric evolution during constant stresses is discussed., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][EUGANIC][EDA Contract B 1447 IAP1 GP][5G_GaN_2]

The reliability of AlGaN/GaN HEMTs adopting Fe and C co-doping, with high and low carbon doping concentration was investigated by means of different stress tests. Firstly, DC and pulsed I-V characterization at room temperature are discussed, then drain step stress tests at different gate voltages are compared, afterwards, the constant stress at different bias points are discussed. Results show that the high C HEMTs showed reduced DIBL, smaller leakage current, as well as decreased electric field, leading to an improved robustness during on-state stress testing, with respect to the reference ones. Failure modes during constant voltage stress consists in a decrease of drain current and transconductance, accelerated by temperature and electric field., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][EUGANIC][EDA Contract B 1447 IAP1 GP][5G_GaN_2]

We present an extensive analysis of the trapping processes induced by drain bias stress in AlGaN/GaN high-electron-mobility transistors (HEMTs) with p-GaN gate. We demonstrate that: (i) with increasing drain stress, pulsed I-V and VTH measurements shown an initial positive VTH variation and an increase in RON then, for drain voltages >100 V, VTH is stable and the RON shows a partial recovery. (ii) At moderate voltages, VTH instability is related to trapping at the gate stack, due to residual negative charge left behind by the holes that leave the p-GaN layer through the Schottky gate contact and/or to trapping at the barrier. At higher voltages, we demonstrate the interplay of two trapping processes by C-V and pulsed drain current analysis: (iii) a fast storage of positive charge, accumulated near the buffer/SRL interface, not strongly thermally activated, dominating at higher voltages; (iv) a slower negative charge storage, thermally activated with activation energies for trapping and de-trapping equal to ~0.6 eV and ~0.4-0.8 eV, respectively., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][European Union's Horizon 2020 research and innovation program][InRel-NPower][grant agreement No. 720527]

The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of the p-GaN layer. The analysis was carried out by comparing the main DC parameters of devices that differ in surface cleaning process of the gate trench, gate dielectric thickness, and body layer doping. . On the basis of experimental results, we report that: (i) a good cleaning process of the etched GaN surface of the gate trench is a key factor to enhance the device performance, (ii) a gate dielectric >35-nm SiO2 results in a narrow distribution for DC characteristics, (iii) lowering the p-doping in the body layer improves the ON-resistance (RON). Gate capacitance measurements are performed to further confirm the results. Hypotheses on dielectric trapping/detrapping mechanisms under positive and negative gate bias are reported., Comment: 5 pages, 10 figures, submitted to Microelectronics Reliability (Special Issue: 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2020)

In the experimental electroluminescence (EL) spectra of light-emitting diodes (LEDs) based on N-polar (In,Ga)N/GaN nanowires (NWs), we observed a double peak structure. The relative intensity of the two peaks evolves in a peculiar way with injected current. Spatially and spectrally resolved EL maps confirmed the presence of two main transitions in the spectra, and suggested that they are emitted by the majority of single nano-LEDs. In order to elucidate the physical origin of this effect, we performed theoretical calculations of the strain, electric field, and charge density distributions both for planar LEDs and NW-LEDs. On this basis, we simulated also the EL spectra of these devices, which exhibit a double peak structure for N-polar heterostructures, both in the NW and the planar case. In contrast, this feature is not observed when Ga-polar planar LEDs are simulated. We found that the physical origin of the double peak structure is a stronger quantum-confined Stark effect occurring in the first and last quantum well of the N-polar heterostructures. The peculiar evolution of the relative peak intensities with injected current, seen only in the case of the NW-LED, is attributed to the three-dimensional strain variation resulting from elastic relaxation at the free sidewalls of the NWs. Therefore, this study provides important insights on the working principle of N-polar LEDs based on both planar and NW heterostructures.

We investigated the origin of the high reverse leakage current in light emitting diodes (LEDs) based on (In,Ga)N/GaN nanowire (NW) ensembles grown by molecular beam epitaxy on Si substrates. To this end, capacitance deep level transient spectroscopy (DLTS) and temperature-dependent current-voltage (I-V) measurements were performed on a fully processed NW-LED. The DLTS measurements reveal the presence of two distinct electron traps with high concentrations in the depletion region of the p-i-n junction. These band gap states are located at energies of $570\pm20$ and $840\pm30$ meV below the conduction band minimum. The physical origin of these deep level states is discussed. The temperature-dependent I-V characteristics, acquired between 83 and 403 K, show that different conduction mechanisms cause the observed leakage current. On the basis of all these results, we developed a quantitative physical model for charge transport in the reverse bias regime. By taking into account the mutual interaction of variable range hopping and electron emission from Coulombic trap states, with the latter being described by phonon-assisted tunnelling and the Poole-Frenkel effect, we can model the experimental I-V curves in the entire range of temperatures with a consistent set of parameters. Our model should be applicable to planar GaN-based LEDs as well. Furthermore, possible approaches to decrease the leakage current in NW-LEDs are proposed., Comment: 10 pages, 9 figures