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The 7th generation Jacinto™ SoC platform is an evolution of prior architectures [1], [2] and integrates new capabilities to support a wide set of applications, including automotive, industrial, and broad market. This drives a diverse set of requirements which need IP innovation and new techniques across the entire SoC stack including: high-reliability techniques for automotive, including circuit analysis and screening; new IP development including new DSP, signal processing and data movement architectures; embedded vision, machine learning, and imaging and video acceleration; new security and safety innovations, including an integrated safety MCU; dedicated security controller, and hardware features to enable ASIL-D support. This SoC platform and first implementation also integrates techniques for simplified power-supply management and support for cost-sensitive systems through on-die micro-architecture solutions.

A 600-MHz VLIW digital signal processor (DSP) delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates (MMACs) at 0.3 mW/MMAC (16 b). The chip has 64M transistors and dissipates 719 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an eight-way VLIW DSP core, a two-level memory system, and an I/O bandwidth of 2.4 GB/s. The chip integrates a c64X DSP core with Viterbi and turbo decoders. Architectural and circuit design approaches to achieve high performance and low power using a semi-custom standard cell methodology, while maintaining backward compatibility, are described. The chip is implemented in a 0.13-/spl mu/m CMOS process with six layers of copper interconnect.

The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.

The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2/spl trade/ Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17 mW/MMAC (8 bit). The chip is implemented in state of the art 90 nm CMOS technology with 7-layer copper metalization. The core dissipates 1080 mW at 800 MHz, 1.2V. The system-on-chip is targeted for high performance wireless infrastructure application. It has an 8-way VLIW DSP core, a 2-level memory system, and an I/O bandwidth of 3.2GB/s.

As frequency and processing capabilities of today's Digital Signal Processors (DSPs) are increasing, so is the needed data rate to fully utilize the available processing bandwidth. Moreover, high-end applications may require multiple DSP's on a single chip, further pushing the data rate requirements. There are varying external devices with which the processors may wish to communicate concurrently. A 'plug and play' like approach for external devices and a scalable high-performance multi-processor data rate solution would be highly desirable. In this paper, a scalable, high performance Direct Memory Access (DMA) architecture for all on-chip and off-chip data communication between multiple processors and various external devices is proposed. This architecture has been implemented on Texas Instruments TMS320C6211 C6x DSP.