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Numerous areas of VLSI Design and Automation including test and diagnosis have already started benefiting from machine learning based approaches. In this paper, we focus on application of machine learning techniques in the context of Volume Diagnosis methodology which aims at improving the yield analysis and management process. Specifically, we apply machine learning to monitor and predict throughput bottlenecks in diagnosis process that impede the pace of yield analysis. In the proposed supervised machine learning technique, diagnosis features extracted from thousands of devices are used to train a random forest regression model and features causing greatest impact on run times are predicted. This technique has resulted in identifying a class of faults (labelled “hyperactive faults”) to be strongly correlated to diagnosis run time. Based on this finding, we propose improvements to volume diagnosis methodology to identify and mask hyperactive faults in advance from volume diagnosis process. Experimental results using proposed improvements on large industrial designs demonstrate up to ~8% reduction in volume diagnosis run time with no loss of accuracy and resolution.

Need for competitive part with reduced cost of build is pushing the boundaries of scan compression adoption in high volume designs. This opens up multiple challenges in effective failure diagnosis, especially in deep sub nanometer designs with higher defect densities and higher probabilities of multi-defect failures. While there are many conventional methods available to address this challenge, they largely suffer from poor accuracy or are time intensive; more particularly at higher scan compression. In this paper, we present a new robust multiple defect diagnosis algorithm and methodology, aimed at achieving high accuracy and resolution in the presence of multiple defects independent of the compression solution implemented. We also present summary from a detailed evaluation conducted to study the efficacy of the proposed diagnostic methodology. Experimental results on a 45nm industrial design indicate significant improvement in accuracy and resolution at 450X high scan compression using the proposed methodology.

Traditional software-based scan chain diagnosis methodology requires failures from scan chain shift pattern(s) and a few logic patterns to identify the location of defective flop(s). The number of failures required for this methodology is massively high and collecting such magnitude of failures may not always be practical in a volume diagnostic environment. This problem is further exacerbated by the increased usage of low cost testers with limited tester fail buffer. Furthermore, the diagnosis of these massive failures is extremely time consuming due to expensive simulation iterations required for identifying the defective flop(s). In this paper, we propose 3 enhancements to an existing hardware-based scan chain diagnosis technique defined for FULLSCAN test mode to make it successful in a volume diagnostic environment. These include: 1) extension for compression modes 2) reduction of failures required for diagnosis by minimizing the expect values in patterns 3) novel Multiple Device Diagnosis (MDD) algorithm and methodology to diagnose 1000s of failing devices in a single run. Experiments conducted on industrial designs on randomly chosen failing devices demonstrated up to 19.68X speed-up using the proposed MDD algorithm.

Volume Diagnosis is a proven methodology to significantly improve the yield enhancement rates. One of the key factors of success to this methodology is being able to perform diagnosis on hundreds to thousands of failing dies using a limited amount of computational resource in a tractable time. This paper presents a new Multiple Device Diagnosis (MDD) system to significantly improve the throughput of volume diagnosis by performing logic diagnosis on a group of failing devices. Experiments conducted on large industrial designs with randomly selected groups of failing devices demonstrated up to 12X increase in speed-up with the proposed system.

This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM architecture to map SoC level failures to a particular embedded core. These TAM architectures allow high level of diagnosis resolution and performance.