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A single-inductor multiple-input multiple-output converter is proposed in this paper that can be used in low-power systems due to low output current and voltage. This converter is implemented discretely, and only one microcontroller is employed to control the system. The unique zero-current switching (ZCS) technique considered in this paper is such that only by reading the inductor’s left-side voltage the optimal value of the inductor discharge duty cycle is determined. This method can be generalized to low-power and high-power converters, whether implemented and designed as discrete or integrated. This converter works in discontinuous conduction mode. It uses pulse width modulation control and the time-multiplexing control method, which makes the system have high efficiency and makes the cross-regulation problem between the converter’s outputs tiny. The control algorithm considered in this converter is digital, which determines the optimal charge and discharge duty cycles. Also, the switching frequency of this converter is constant, relatively low, and equal to 5[Formula: see text]kHz. The efficiency of this converter has reached 91.6% by using the ZCS technique and other mentioned control methods.

This paper proposes a novel method for the image interpolation problem based on two-dimensional discrete wavelet transform (DWT) with the edge preserving approach. The purpose of this method is to consider two contrasting issues of over-smoothing and creation of spurious edges at the same time, and offer a novel solution based on statistical dependencies of image sub-bands, and noise behavior. The offered method has a multi-faceted approach for the problem; by sub-band coding, it handles each 2D-DWT image sub-band with a different solution. For LH and HL sub-bands, two algorithms work together in order to preserve regularity. Area_Check algorithm is a four-phase edge-preserving algorithm that aims to recognize and interpolate separating lines of environments and edgy regions in the best possible way. On the other hand, RLS_AVG algorithm interpolates smooth surfaces of the image by keeping the regularity of the image without over-smoothing. In this regard, the offered algorithm has a great power to counter jaggies and annoying artifacts. In the end, in order to demonstrate the capability, and performance of the proposed method, the final results in various metrics are compared with the results of the most famous and the newest image interpolation methods.

This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estimator. The presented multiplier-less hardware uses a combined coefficient selection and shift-and-add implementation (CCSSI) unit in order to prevent multiplications in FFT computation. Two filtering operations, which are implemented in folded architecture, are utilized. The micro-rotation resources of the CCSSI unit can be shared with estimator’s modules simultaneously. The proposed architecture is a nonparametric estimator that operates based on a modified, memory-based, 128-point scalable radix-22 FFT processor. It uses bidirectional fractional delay filter to estimate half delay sample in merging two FFTs. Using modified safe-scaling, the final output would be valid, without any averaging operation. Another important feature of the proposed method is its capability of operating in short word lengths (WL). Artix-7, as an ideal option for DSP applications, is the utilized FPGA in this research. As results demonstrate, the hardware has a high capability in operating in short WLs which results in high performance in low-power applications.

In this paper, we present a rectification process through electron emission from sharp tips under a high electric field of 109–1010 V/m based on the Fowler–Nordheim theory. A large planar array of ...

A rectification concept based on field electron emission in a nanoantenna is proposed. The device consists of three parts, i.e., an aspherical micro-lens, a nanoantenna, and an electron collector e...

In this article, a low phase noise quadrature VCO (QVCO) is proposed, which uses superharmonic injection and current reuse techniques to reduce phase-noise and power consumption. The LC tank circuit quality factor is improved, using a negative resistance. PMOS transistors have also been used instead of NMOS transistors. As a result of these modifications, further phase noise reduction is achieved. The QVCO consists of a VCO operating at 2ω0 (twice the operating frequency) injecting its output signal into the common source nodes of two other oscillators operating at ω0. Using this superharmonic injection technique, in addition to phase noise reduction, the chance of injection pulling caused by powerful PA signals is reduced. Also, the current reuse technique automatically adapts its voltage to the requirement of the supplied stages, therefore, it is not limiting the VCO output swing. Designed for the 900 MHz band and simulated in a 0.18 µm CMOS technology with 1.8 V power supply, the circuit achieves a phase noise of − 141.5 dBc/Hz at 1 MHz offset frequency, while consuming 12.8 mW power. The proposed circuit is compared with several re-simulated previously published work. The comparison shows 17.5 dB reduction in phase noise compared to conventional P-QVCO, while consuming the same amount of power.

A low-power and low-noise bioamplifier for multichannel electrode arrays (MEA) is presented. Reduction in area and power is achieved (1) by means of active-integration using a small capacitor, (2) implementation of a high-pass filter without using large DC-blocking capacitors, and (3) by sharing the common parts of bioamplifiers of different channels. This bioamplifier, as the main building block of a neural recording system, has been designed to record neural signals, amplify them, filter out the unwanted signals, and extract the action potentials. Theoretical analysis on noise specification, crosstalk between the channels due to sharing parts, and power reduction has been presented and a design trade-off is achieved. Following the theoretical analysis, a 4-channel bioamplifier has been designed and simulated in 0.18 μm CMOS technology, in total layout area of 0.0976 mm2 and the current consumption of 3.2 μA per channel from ±1.2 V power supply. Based on post-layout simulation results, the power and noise specifications of the proposed design are comparable with the best specifications reported to date based on noise efficiency factor (NEF). The bioamplifier achieves a mid-band gain of 60 dB and a -3 dB bandwidth from 100 Hz to 10.2 kHz. The input-referred noise is 3.87μVrms corresponding to a NEF of 2.65, for the mentioned -3 dB bandwidth.

This paper presents A CMOS Gain Controllable Low Noise Amplifire (LNA) in TSMC 180nm process. A gain control circuit is exploited and added in the first stage of a folded cascode LNA to achieve gain tuning. Resistor and capacitor feedback technique are introduced for improving IIP3 and input matching. Without gain controlling, located in the frequencies of interest (5.24 GHz), the gain is 27.54 dB, and the NF is 1.97 dB, and S11 is -25.44 dB with a good IIP3 of +3.14 dBm at 1.8 V supply.

A wide bandwidth integer-N Type-I PLL is proposed in this paper. By using a novel Delay-line based filter as loop filter, presented PLL achieves a loop bandwidth about 5 times greater than that of standard type-I PLL. The chosen strategy in widening the PLL bandwidth is to replace the RC loop filter with a 2-tap delay-line based filter which provides a desired magnitude and phase response. Presented PLL obtains a loop bandwith of about 5MHz with an input reference frequency of 10MHz, and also -50dBc spur level is achieved. - 119 dBc/Hz in-band phase noise at 1MHz offset is obtained from simulation. PLL total power consumption is 2.5mW from the nominal supply of 1.8V.

A single-inductor multiple-output (SIMO) converter with constant frequency auto-buck-boost feature is presented in this paper. This converter can supply more than one output. Some applications of this converter include their use in mobile phones and medical devices that require different voltages. This paper deals with a single-inductor dual-output (SIDO) converter for simplicity, which can be generalized to multiple outputs. Here, according to the mode in which the converter works and the maximum load current, which is about 1 rnA, the outputs work completely independent, which means changing the load in one output does not affect the other output. The converter operates in discontinuous conduction mode (DCM), and the time-multiplexing control (TMC) method and pulse width modulation (PWM) are used in its controller. An analog to digital converter (ADC) is used to monitor the output voltage. The switching frequency in this converter is 5 kHz, and due to the possibility of changing the load at the output, the optimal duty cycle value for each output channel is set by the measured voltage. In this paper, the goal is to generate stable voltage and reduce cross regulations to the minimum possible value or even to zero and consider regular timing for switches by the controller.

This paper introduces a 1.2GHz adaptive bandwidth Type-I PLL with wide bandwidth. PLL operates in wide bandwidth mode during transient to have a fast settling time, and in narrow bandwidth mode during phase lock to more efficiently suppress the sidebands at f ref , 2f ref , etc, at VCO output. The PLL operating mode selection is done utilizing the digital lock detector circuit. The bandwidth of proposed PLL in transient is 5–10 times greater than the bandwidth of traditional Type-I PLL. Operating with a reference frequency of 10MHz, the proposed PLL provides a loop BW of 5MHz in transient, and a spur level of −53dBc. The presented PLL exhibits an in-band phase noise of -118 dBc/Hz at 1MHz offset. PLL total power consumption is 2.5mW.

In this paper, a new analog CMOS current-mode divider is presented based on a new voltage controlled resistor. The proposed divider can be used in analog computation, fuzzy logic controllers (FLC), neural network, etc. The advantages of the improved structure are simplicity, wide bandwidth, wide dynamic range, low supply voltage requirements, low-power consumption and low active area. The post-layout simulations of the proposed divider implemented in a 0.18-□m CMOS process was performed with HSPICE software. In this case, supply was 0.9-V and divider has less than maximum 1% linear error. Also, the total power consumption was 42-□W at more than 350-MHz bandwidth and occupied area was about 370-□ $m^{2}$ .

This paper presents an eight-phase LC voltage controlled oscillator (VCO) using a super-harmonic coupling technique. Eight various phases are created in which there is 45 degrees phase difference between continued outputs. Four oscillators are coupled by two nmos transistor used in each stage acting as a mixer to generate proper second harmonic signals. Second harmonic signal is injected to the center tap of the tank inductor in the next stage. The proposed VCO is simulated in silterra $.18\ \mu\mathrm{m}$ BCD process with the area of $.7\times 0.7\ \mathrm{mm}^{2}$ . The VCO can be tuned from 22.2 GHz to 25.1 GHz, a frequency tuning range of 12.3% at 1.8V supply. With each VCO consuming 2.2 mW DC power (8.8 mW total), the phase noise is −107 dBc/Hz at 1 MHz offset when VCO output frequency is 24 GHz. Maximum FOM of the proposed VCO is 190.16 dB. Comparison results show that the proposed VCO is among the best works.

A two-stage wideband low-noise amplifier (LNA) using source-follower feedback (SFF) is presented. A novel approach using a combination of asymmetrical inductive peaking and SFF is used to alleviate the trade-off between input matching and noise figure, thus making more space for design. A peaking inductor in the gate of the NMOS in the first stage is added to resonate with the capacitance of the node, resulting better input matching. In addition, a second stage is added to widen gain bandwidth using inductive load. Simulated in TSMC $\mathbf{0.18}-\mu\mathbf{m}$ CMOS technology for 1-6.7 GHz, voltage gain of 12.5 dB and a NF of 2.2dB over the 3-dB bandwidth is achieved. The LNA consumes 9.3 mW from a 1.8 V supply.

This paper presents an 8-bit Time-to-Digital Converter (TDC) based on Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) architecture. The proposed multi-stage architecture converts a time interval to a voltage and then delivers it to a SAR ADC for voltage-to-time conversion. Unlike other SAR ADC architectures, this structure is not complicated and does not use a high number of capacitors. This design includes several parts like comparator and subtractor that are designed optimally. In this work, quantization noise is decreased by first-order noise shaping. The conversion rate of the proposed SAR TDC is 200 MHz, and the TDC resolution is 5ps. The proposed schema is designed and simulated in a standard $.18\mu\mathrm{m}$ CMOS technology and consumes a maximum of 6mW power from a 1.8 V supply.

In this paper, using an additional oscillator that operates at twice the main output frequency, super–harmonic coupling is created between two LC cross–coupled oscillators. The additional oscillator output signals are injected into the two main oscillators in a special way, such that in addition to forcing those oscillators to work in quadrature mode, a tail current shaping technique is performed on them, through the same circuit path. As a result, the main oscillators output phase noise is reduced. The second harmonic signals with the help of two additional NMOS transistors shape the gate voltages and consequently the drain current of the tail transistors. The quadrature mode operation of the proposed circuit is mathematically proved and the intrinsic tail current shaping behavior of it is analyzed. The proposed QVCO is designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V and a total power consumption of 4.4 mW at 2 GHz center frequency with 5.5% tuning rage. Simulation results confirm the proposed quadrature mode operation. It also shows the phase noise of −128.1 dBc/Hz for the proposed QVCO at 1 MHz offset and 1.92 GHz carrier, which is 9.3 dB better than that of the conventional Parallel (P)–QVCO. The maximum phase error for 0.5% I and Q tank capacitor mismatch is 1.47°.

Rectifiers are an integral part of power harvesting systems. In this paper, the literature on RF power rectifiers is surveyed, starting from the well-known voltage doubler. Effects of using low turn-on voltage devices on forward and reverse losses, and therefore, on conversion efficiency, is discussed. Samples of rectifiers with external devices, such as Schottky diodes are presented. Idea of external Vth cancellation through a rechargeable battery, self Vth cancellation, and floating gate transistors with charge injection onto the gates are demonstrated. Then, standard bridge rectifier and its modified versions, including Vth cancellation technique, are explained. Using low voltage devices in other technologies, such as silicon on sapphire and silicon on isolator are also discussed. After literature survey, the bridge rectifier is studied in detail, to extract guidelines for efficiency enhancement. Bridge rectifier has high PCE, because the transistors have a dynamic bias that lowers their forward and reverse losses, simultaneously. Then, the effect of transistor threshold voltages on the bridge rectifier performance is investigated. We propose to shift peak region in the efficiency curve to a desired output voltage, based on which, two modified rectifiers are introduced. A single stage modified bridge rectifier is proposed with 3.3 V transistors, that achieves efficiency of around 80% at 0.9 V output. Then, a two stage modified bridge rectifier is proposed, that uses a combination of 1.8 and 3.3 V transistors to remove the need to source-bulk connection in NMOS transistors (that requires triple-well CMOS technology). Simulations predict around 80% efficiency at 1.7 V output.

In this paper, using the concept of impulse sensitivity function (ISF) in Hajimiri's phase noise model, a novel circuit method for phase noise reduction in LC cross coupled oscillators is proposed. Based on the proposed technique, at outputs zero crossing points, where ISF is maximum, current supplying to the transistor pair is stopped by two added transistors. Due to the shaped effective ISF waveform and also reduction of its RMS value, phase noise is decreased. In addition, the cascode structure of the proposed technique leads to more phase noise reduction due to the suppression of the transistors noise power. The proposed circuit is designed for 10 GHz output frequency and inductor quality factor of 12, and simulated in a standard 0.18 µm CMOS technology with a 1.8 V supply. Compared to the simple cross coupled oscillator, phase noise at 1 MHz and power consumption are reduced by 8 dB and 26%, respectively. The phase noise and FOM for the proposed oscillator at 1 MHz offset frequency are ýý107.8 dBc/Hz and 186.2 dB, respectively.

In this paper, a low phase noise oscillator using tail current shaping method is presented. The current shaping is achieved using two paths for current disconnection and current injection, as a result of which, the total tail current is shaped to a sharp and sawtooth waveform, close to an impulse. Each switching transistor is ON only in 22% of an oscillation period, and tail current is mostly supplied to these transistors near the outputs peak points. In those moments, the oscillator sensitivity to noise sources is minimum. The proposed oscillator is designed and simulated in 0.18 μm RF CMOS technology with 1.8 V supply, and using the inductor model offered by the process, with quality factor of 11. Post layout simulations predict an oscillation frequency of 1.65 GHz, and phase noise of −127.7 dBc/Hz at 1 MHz offset, which is 6.3 dB better than that of simple cross coupled oscillator with the same core oscillator power consumption of 2.2 mW. The proposed circuit, however, consumes an extra power of about 1.9 mW for the added current shaping circuits. Compared to conventional tail current shaping technique, the proposed oscillator offers better tail current shaping, and a much higher start-up current and gain, which is desirable.

Tail current shaping is a known technique for phase noise reduction. According to this technique, close to outputs zero crossing points, where Impulse Sensitivity Function (ISF) is maximum, current supplying path to the transistor pair is disconnected. In this paper, tail current shaping is performed by two additional transistors that are placed in cascode configuration with the tail current source. Conventional tail current shaping is performed by two tail transistors with the gates connected to the oscillator outputs. The proposed circuit outperforms the conventional circuit in phase noise performance, due to four mechanisms: higher impedance seen from the common source of switching transistors due to cascode current source; better tail current shaping; higher oscillation amplitude with the same power consumption; and lower RMS value of the effective ISF. Also, the proposed circuit presents more stable bias point and output amplitude, compared to conventional circuit. In addition, higher ratio of start-up tail current to the minimum of shaped tail current for the proposed circuit, removes the need for additional start-up detection circuits. Post layout simulations predict a sample oscillator designed at 4 GHz in 0.18 µm RF CMOS technology presents 11.3 and 3.8 dB less phase noise at 1 MHz offset, compared to simple and conventional oscillators, respectively.

In conventional charge-pump PLLs, if the third high-frequency pole is ignored, the system comprises of two poles and a zero. The transfer function of such a system is second-order low pass, which in some part of its frequency spectrum, the amplitude response | H | goes above unity. This translates to jitter-peaking, which in turn amplifies the input phase noise. Depending on damping factor or ζ , this jitter-peaking could be large or small. In this paper, a dual-path PLL with an additional Voltage Controlled Delay Line (VCDL) is presented that removes the jitter-peaking by adjusting the frequency values of the zero and poles in the PLL transfer function. In this new architecture, by increasing the VCO's gain ( K vco ) the output phase noise is reduced. Designed and simulated in 65 nm CMOS and operating with a reference frequency of 12.5 MHz, the proposed PLL provides a spur level of −45dBc. The presented PLL exhibits an in-band phase noise of − 117 dBc / Hz at 1 MHz offset and total power consumption of 10.5 mW.

In this work, the operation mechanism of the Connected-Sources Parallel Quadrature Oscillator (CSPQO) is investigated meticulously through a novel perspective. It is proven that, unlike Disconnected-Sources Parallel Quadrature Oscillator (DSPQO), conduction angles of the switching and coupling transistors vary versus the coupling factor in CSPQO. This perspective leads to formulating CSPQO's drain currents to derive closed-form expressions for its phase noise for the first time. A comprehensive phase noise analysis for CSPQO is presented using Hajimiri's phase noise theorem. There are less than 2% and 1dB errors for oscillation amplitude and phase noise calculations. Besides, an inclusive comparison is performed between DSPQO and CSPQO, and it is established that CSPQO has a better performance for coupling factors less than 1. It is shown that a coupling factor of 0.35 is an optimum design point for CSPQO to have better phase noise and Figure of Merit (FoM) performances compared to DSPQO.

The conventional method for image impulse noise suppression is standard median filter utilization, which is satisfying for low noise densities, but not for medium to high noise densities. Adding a noise detection step, as proposed in the literature, makes this algorithm suitable for higher noises, but may degrade the performance at low noise densities. An adaptive switching median-based (ASM) algorithm has been used in this paper for noise suppression. First, the algorithm is modified to achieve a higher PSNR, especially for low noise densities. Then, the structure of the modified algorithm is improved to obtain higher operating speed in hardware implementation, for real-time applications. The implemented algorithm works in two steps, detection and filtering. The noise detection method is enhanced, by merging the amount of memory used for the algorithm implementation. As a result, less hardware resources are required, while the chance of false noise detection is reduced, due to the improvement made in the algorithm. In the filtering step, an adaptive window size is used, based on the measured noise density. This improved algorithm is adopted for more efficient hardware implementation. In addition, high parallelism is utilized to boost the operating frequency, and meanwhile, clock gating is used to lower power consumption. This architecture, then, has been implemented physically on an FPGA, and an operating frequency of 93 MHz is achieved. The hardware requirement is approximately 10,000 4-input LUTs, and the processing time for a 512 × 512 pixels image is measured at 12 ms.

A novel technique for reducing phase noise of LC cross coupled oscillators is proposed, using second harmonic filtering of the tail current noise. Using a LC network in between tail current and switching transistors, second harmonic of the tail current noise is filtered out. The filtering circuit works simultaneously as low pass and band stop filters. Therefore, output phase noise is reduced. Three circuits including basic cross coupled oscillator with tail current, and two cross coupled oscillators with conventional and proposed method of tail current noise second harmonic filtering are designed and simulated in 0.13m CMOS technology, with the same power consumption from 1.2V supply. Simulation results show that for the proposed circuit, at 2GHz frequency and 1MHz offset, phase noise and Figure of Merit (FoM) are 130dBc/Hz and 192.3dB, respectively. Compared to basic and conventional circuits, proposed method presents phase noise improvements of 13dB and 7.5dB, respectively, at the cost of increased die area, due to the filtering inductor. Display Omitted

In this work, one of local stereo vision algorithms named SAD approach, which is used in image depth estimation, has been surveyed, and an efficient and real-time new hardware implementation has been proposed. The proposed method has been verified and tested using C implementation. The acceptable simulation results along with the detailed explanation of numerous pre-processing steps are also presented. Our innovations could be divided into two sections: architecture and algorithm. In architecture section, by using a specific architecture, memory access has been lowered and therefore, speed has been increased. In algorithm section, a part of local algorithm, known as refinement, has been substituted with a simpler and more efficient algorithm. Cyclone IV has been utilized as our hardware platform. In this article, this point would demonstrate how to use an exact but less complicated controller, which results in less area, and how to use pipeline architecture and remove repetitive and redundant memory accesses, which conduct our stereo vision system to meet the real-time constraints. Suggested hardware implementation could reach to 53fps processing speed with 100MHz clock. No processing IP core has been used. In comparison with related work, our proposed method is more efficient in logic elements usage, and accordingly in power consumption.

In this paper, a novel method of Super–Harmonic coupling is proposed to generate quadrature outputs. In this method, by direct connection of all switching transistors bulk terminals, a second harmonic current is injected from each one of the I/Q oscillators to the other. Therefore, the proposed circuit is called Body–Injected Super–Harmonic coupling (BISH–) QVCO. The quadrature operation of the proposed circuit is mathematically proven and certified by simulations. In addition, through a detailed analysis, closed–form expressions are derived for the output phase noise and phase error. To have a fair performance evaluation of the proposed topology, the proposed BISH-QVCO, and the conventional P–QVCO are designed and simulated in 0.18 ​μm RF-CMOS technology with 3.22–3.64 ​GHz oscillation frequency (12.25% tuning range), a power supply of 1.8V, and the same power consumption of 3.85 ​mW. The quality factor of the tank circuits is calculated as 9.2. Post layout simulation results predict phase noise of −122.3dBc/Hz at 1 ​MHz offset from 3.64 ​GHz oscillation frequency that presents 4.1 ​dB and 2.7 ​dB phase noise improvements compared to the conventional P–QVCO and simple LC VCO, respectively. The maximum I and Q outputs phase error due to a 2% tank capacitor mismatch is 7°. A FOMT of 189.4 ​dB is achieved for the proposed QVCO. Also, the proposed method is capable of generating multi–phase outputs, which can be ranked among the well-performing ones.

In this paper, a novel passive super–harmonic coupling QVCO is presented. The coupling is achieved by Cross–Connecting the top and bottom Common–Source nodes in the complementary (current reuse) LC Cross–Coupled oscillator topology, and therefore, the circuit is named as C3S–QVCO. Unlike the transformer coupling QVCO (TC–QVCO), as the typical super–harmonic coupling technique, the die area is not increased. Also, in the proposed QVCO, neither additional power consumption nor additional noise generator component is required, for quadrature operation. Therefore, the proposed QVCO has a good power consumption performance. The proposed method is evaluated theoretically and analytically, and it is proved that the proposed method is capable of generating multi–phase outputs. The proposed QVCO is designed in a 0.18 ​μm RF–CMOS technology with a power supply of 1.8 ​V, the current consumption of 6.25 ​mA, and the tuning range of 3.75–3.95 ​GHz (5.3%). Post layout simulation result shows −129 ​dBc/Hz, and 190 ​dB phase noise and FOM for the proposed QVCO at 1 ​MHz offset from the 3.75 ​GHz frequency. The proposed QVCO presents 6 ​dB phase noise improvement compared to parallel (P)–QVCO and also demonstrates similar phase noise performance to that of the TC–QVCO, with the same power consumption. Maximum phase/amplitude errors of the proposed QVCO for a 1% mismatch in the oscillator’s tank capacitors are 0.72°/2 ​mV, in the whole tuning range. Those are 0.77°/7.3 ​mV for the P–QVCO and 1.3°/2.3 ​mV for the TC–QVCO.

The quality of service for the cell-edge users is degraded by inter-cell interference, preventing fulfillment of the LTE-A requirements. The effects of the cell-edge interference can be suppressed by Coordinated Multi-Point (CoMP) transmission/reception techniques. One approach of CoMP in downlink scenario is joint transmission (JT), which is closely related to MIMO communication concept. This leads to incorporation of conventional MIMO detectors for JT. MIMO tone by tone detection demands an extensive computational power. Recently, interpolation based MMSE MIMO detectors have been proposed to reduce the computational power. In this work, the recently proposed floating-point interpolation based MMSE detector is modified to make it suitable for fixed-point implementation. The optimal word-length is determined by simulation-based optimization. The proposed algorithm is implemented on a Virtex-7 FPGA and achieves a clock frequency of 422 MHz, with an optimal word-length of 20 bits. The throughput of the implemented detector exceeds 1.15 Gbps with 0.6 μs latency.

The sorting algorithms have found applications in various research fields including image and video processing. High speed sorting is important in real-time applications, such as real-time image processing. Two properties are criterion for sorting networks: the number of steps (speed) and the number of comparators (efficiency). In this paper, we have proposed a method to decrease the number of steps. We introduce a new method for sorting an unordered sequence, which is based on the graph theory concept,and contrary to the conventional sorting networks, it consists of graph edge calculators rather than compare-and-swaps. An outstanding feature of the proposed method is that for small number of inputs, its number of steps is independent of the number of inputs that denotes it orders N inputs in O(1) steps. Moreover, the proposed method surpasses the previous ones in term of speed; it just needs two steps to sort a sequence. In the first step, all the inputs are compared with each other, and in the second step, the results of comparisons direct the inputs to the right outputs. To justify the functionality, the proposed method is simulated with the Modelsim-Altera and implemented on a Cyclone IV FPGA platform. Simulation results indicate that in comparison with the Bather's Bitonic mergesort, which is known to be the fastest algorithm, the proposed method while requires 80% more LEs, consumes 52% less memory and achieves 73% more throughput. Furthermore, the Bitonic mergesort can only accept a power of 2 number of inputs, while the proposed method does not hold such a limitation.

This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a power spectral density (PSD) estimator, based on the Bartlett method, for low-power biomedical applications. The Bartlett method is a nonparametric method for PSD estimation. The proposed architecture operates based on a modified multiplierless 64-point optimized radix-22single-path delay feedback (R22SDF) FFT processor. To obtain the final result, it also uses modified safe-scaling in a way that removes the need to use several extra hardware units. It takes advantage of combined coefficient selection and shift-and-add implementation (CCSSI) for computing twiddle factors which is a new algorithm based on digital computer coordinate rotation (CORDIC) for generating trigonometric values. The proposed method has the capability of operating on short word lengths (WLs). Artix-7 is the FPGA used in this research and Verilog is the language used for hardware design. For 8-bit WL and 244-mW power, a frequency of 286 MHz has been achieved. Several vital signals are used for performance comparison of the proposed technique with state-of-the-art designs.

In this paper, a novel super-harmonic coupling technique for generating quadrature outputs is presented using complementary LC cross-coupled structure as the core oscillator. It is performed by connecting the top tail transistor gate terminal of the I oscillator to the bottom common-source node of the Q oscillator, and vice versa. Therefore, the second harmonic currents are injected through each tail transistor to the core oscillator with antiphase relation. The quadrature operation of the proposed QVCO are mathematically proved and its phase noise and phase error performances are investigated analytically. The proposed and conventional parallel (P)-QVCO are designed at the frequency range of 4.12-4.34GHz in $0.18\mu\text{m}$ CMOS technology with same power consumption of 4.75mW. The technology offered symmetrical spiral inductors are used in all tank circuits with a quality factor of 12. The two QVCOs are simulated using Cadence Spectre-RF simulator with same sizing and power consumption. The simulation results confirm quadrature operation of the proposed QVCO and show -125.1dBc/Hz phase noise at 1MHz offset from 4.12GHz carrier frequency for the proposed QVCO, that compared to the P-QVCO, 7.3dB phase noise improvement is achieved. The maximum phase errors of the proposed and conventional QVCOs are 4.6° and 3.15°, respectively for 1% tank capacitor mismatch. The proposed QVCO has a FOM of 190.6dB.

This paper proposes a new super-harmonic coupled quadrature voltage controlled oscillator (QVCO), which oscillates at carrier frequency of 5.4GHz. The structure of the proposed circuit includes two complementary cross coupled oscillator with an extra frequency doubler circuit using mixing operation of triode region transistors to generate anti-phase second harmonic signals. Second harmonic injection takes place at center tap of the tank inductor. Simulation result based on a TSMC 0.18-μ $m$ CMOS technology shows −121.4dBc/Hz phase noise at 1MHz offset frequency, which shows 5dB improvement compared to the conventional complementary P-QVCO. In the proposed method, the quadrature accuracy has lower impact on phase noise. The proposed QVCO dissipates 2.5mA from a 1.8V supply and has a FOM of 189.3dB. The maximum simulated phase error is 3.7°in the presence of 1% tank capacitor mismatch.

This paper presents a 60 mV input voltage start-up system for thermoelectric energy harvesting. A new process tolerant inverter cell is proposed, which is functional at supply voltages as low as 60 mV. Using the proposed unit cell, a ring oscillator has been implemented. The ring oscillator is followed by 40 charge-pump stages, an ultra-low-power level detector, and a boost converter. The energy harvesting system can generate an output voltage of 1 V and delivers a maximum power of 4.5 μW from a 60 mV supply. This system has been implemented in a standard 0.18 μm CMOS technology, uses neither zerothreshold voltage (normally-on) negative-channel metal-oxide semiconductor nor microelectromechanical systems switches and occupies 3.3 mm2.