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This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.

The first fully integrated GaN pulse width modulation (PWM) generator for power conversion applications is presented in this paper. The solution is implemented in a 0.5- $\mu \text{m}$ technology, avoiding additional pins and external capacitors for sawtooth signal generation while providing high accuracy. Indeed, the large GaN process spreads are addressed through an innovative dynamic offset compensation approach whose clock signal takes advantage of the PWM signal itself. The proposed PWM generator adopts a 6-V power supply and includes a 25 digital divider to set the PWM frequency at 500 kHz and the minimum and maximum duty cycles at 6% and 94%, respectively. Experimental results on integrated prototypes validated the correct circuit functionality over the temperature range from −40°C to 120°C. As a main achievement, this work demonstrates effective all-GaN integration of complex mixed analog and digital circuits, thus representing a significant advancement in the approaches to overcome the main limitations of GaN devices and enable fully integrated signal processing implementation.

This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard-cells. The proposed approach guarantees that all the CMOS inverters, taken from a standard-cell library, operate with well-defined quiescent current and output voltage, thus allowing the implementation of analog circuits with good robustness against PVT variations. The approach is based on an Analog Body Bias Generator (ABBG) reusable block, similar to the ones adopted in digital applications to cope with process variations, and exploits the bulk terminals of both the p-channel and n-channel MOS transistors of the standard-cell inverter as current and voltage control inputs. The bulk voltages generated by the ABBG are routed to all the standard-cell inverters used for analog functions and allow to set the quiescent current of each cell to a multiple of a reference current and the static output voltage of each cell to half the supply voltage. The full custom design of the ABBG is presented, as well as the design flow to allow the automatic place and route of the proposed standard-cell based analog building blocks. We finally give an example of application trough the design of a fully synthesizable four-stage-gain low-power operational transconductance amplifier (OTA). Both the body bias generator and the OTA have been implemented in a 65-nm CMOS technology. The OTA nominal current consumption is $1.75~\mu \text{A}$ with 0.41- $\mu \text{A}$ standard deviation. Good robustness against supply and temperature variations is also found.

This work presents a two-stage operational transconductance amplifier suitable for sub-1 V operation. This characteristic is achieved thanks to the adoption of a bulk-driven non-tailed differential pair. Local positive feedback is exploited to boost the equivalent transconductance of the first stage and the quasi-floating gate approach enables the class AB operation of the second stage. Implemented in a standard 180 nm CMOS technology and supplied at 0.6 V, the amplifier exhibits a 350 kHz gain bandwidth product and a phase margin of 69° while driving a 150 pF load. Compared to other solutions in the literature, the proposed one exhibits a considerable performance improvement, especially for large signal operation.

RESUMO Objetivo: Realizar uma revisão sistemática para sumarizar o conhecimento relativo à prevalência de burnout entre médicos atuantes na unidade de terapia intensiva. Métodos: Conduzimos uma revisão sistemática nas bases de dados MEDLINE e PubMed® (última atualização em 4 de fevereiro de 2019), com o objetivo de resumir a evidência a respeito de burnout entre médicos atuantes em unidades de terapia intensiva. Incluímos todos os estudos que relatavam burnout em trabalhadores na unidade de terapia intensiva, segundo o Inventário de Burnout de Maslach e, a seguir, triamos os estudos quanto a dados relativos a burnout especificamente em médicos atuantes na unidade de terapia intensiva. Resultados: Encontramos 31 estudos que descreviam burnout em membros da equipe da unidade de terapia intensiva e incluíam diferentes perfis de profissionais de saúde. Dentre estes, cinco estudos se focalizavam apenas em médicos, e 12 outros investigavam burnout em uma mescla de profissionais atuantes na unidade de terapia intensiva, mas forneciam dados à parte relativos aos médicos. A prevalência de burnout teve grande variação entre os estudos (variando entre 18% e 49%), porém diversas discrepâncias metodológicas, dentre elas os critérios de corte para definição de burnout e variabilidade da escala de Likert, impediram uma análise agrupada significativa. Conclusão: A prevalência da síndrome de burnout entre médicos atuantes na unidade de terapia intensiva é relativamente alta, porém heterogeneidades metodológicas significantes exigem precauções na interpretação de nossos resultados. Os níveis mais baixos de burnout relatados parecem mais elevados do que os identificados em estudos que investigaram uma mescla de profissionais da unidade de terapia intensiva. Há uma necessidade urgente de consenso que recomende o uso consistente do Inventário de Burnout de Maslach para triar a presença de burnout a fim de fornecer dados precisos a respeito de burnout entre médicos atuantes na unidade de terapia intensiva.

Capacitance detection is a universal transduction mechanism used in a wide variety of sensors and applications. It requires an electronic front-end converting the capacitance variation into another more convenient physical variable, ultimately determining the performance of the whole sensor. In this paper we present a comprehensive review of the different signal conditioning front-end topologies targeted in particular at sub-femtofarad resolution. Main design equations and analysis of the limits due to noise are reported in order to provide the designer with guidelines for choosing the most suitable topology according to the main design specifications, namely energy consumption, area occupation, measuring time and resolution. A data-driven comparison of the different solutions in literature is also carried out revealing that resolution, measuring time, area occupation and energy/conversion lower than 100 aF, 1 ms 0.1 mm2, and 100 pJ/conv. can be obtained by capacitance to digital topologies, which therefore allow to get the best compromise among all design specifications.

A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed. The solution can be adopted in sub-1 V applications, as it exploits MOSFETS in the subthreshold regime. Oscillators made up of 3, 5, and 7 stages designed in a standard 28-nm technology and supplied by 0.5 V, were simulated. By exploiting a programmable capacitor array, it allows a very large range of oscillation frequencies to be set, from 1 MHz to about 1 GHz, with a limited current consumption. Considering, for example, the five-stage topology, a nominal oscillation frequency of 516 MHz is obtained with an average power dissipation of about 29 µW. The solution provides a tuneable oscillation frequency, which can be adjusted from 360 to 640 MHz by controlling the bias current with a sensitivity of 0.43 MHz/nA.

Theoretical predictions as well as experiments performed at storage rings have shown that the lifetimes of β-radionuclides can change significantly as a function of the ionization state. In this paper we describe an innovative approach, based on the use of a compact plasma trap to emulate selected stellar-like conditions. It has been proposed within the PANDORA project (Plasmas for Astrophysics, Nuclear Decay Observation and Radiation for Archaeometry) with the aim to measure, for the first time in plasma, nuclear β-decay rates of radionuclides involved in nuclear-astrophysics processes. To achieve this task, a compact magnetic plasma trap has been designed to reach the needed plasma densities, temperatures, and charge-states distributions. A multi-diagnostic setup will monitor, on-line, the plasma parameters, which will be correlated with the decay rate of the radionuclides. The latter will be measured through the detection of the γ-rays emitted by the excited daughter nuclei following the β-decay. An array of 14 HPGe detectors placed around the trap will be used to detect the emitted γ-rays. For the first experimental campaign three isotopes, 176Lu, 134Cs, and 94Nb, were selected as possible physics cases. The newly designed plasma trap will also represent a tool of choice to measure the plasma opacities in a broad spectrum of plasma conditions, experimentally poorly known but that have a great impact on the energy transport and spectroscopic observations of many astrophysical objects. Status and perspectives of the project will be highlighted in the paper.

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

A recently obtained warm plasma model is here considered and the speeds of propagation of the discontinuity waves are calculated. These speeds, relative to the fluid, are 0, ±\sqrt{7/15}ε ,±\sqrt{3/5}ε, ±\sqrt{1/3}, where ε is the smallest parameter invariantly related to temperature. Explicit expressions are also shown for the eigenvectors.