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The characterization of multiple mechanically flexible passive and active electronic components, namely on-foil temperature sensor, relative humidity sensor, and ultra-thin microcontroller unit (MCU) integrated circuit (IC) is presented. These components are readily available for Hybrid System-in-Foil (HySiF) integration, which combines the merits of the high-performance silicon chips with the large-area electronics. The 60-nm thin-film resistance temperature detector (RTD) is fabricated on different substrates and the extracted temperature coefficient ranges from 0.002 to 0.003( $\Omega/\Omega$ )/°C. Furthermore, the capacitive relative humidity sensor is fabricated by utilizing a polymeric sensing dielectric material that is compatible with those polyimides used in ultra-thin chip embedding. The $1-\mu \text {m}$ thick sensor achieves a fast adsorption rise time of $\text {54 ms}$ and a spontaneous desorption fall time of $\text {750 ms}$ . For flexible ICs packaging and HySiF integration, microcontroller chips are back-thinned to a thickness of about ${30}~\mu \text {m}$ . The characterization of the MCU after the thinning process step showed undegraded performance of the integrated analog-to-digital converter in terms of linearity. However, a drop in the on-chip temperature sensor sensitivity is observed for the thin chips and significant degradation in the period jitter of the high-frequency RC oscillator is measured. Finally, continuity tests are performed to validate the functionality of the ultra-thin MCUs when embedded using the Chip-Film Patch (CFP) flexible package.

This paper reports on the status of a comprehensive ten-year research and development effort toward hybrid system-in-foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion in and on a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity and form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on- and off-chip implementation of sensor, actuator, microwave, and energy supply components are addressed.

Current electronic systems and circuits possess approximately 80 % of passive components. Thus, high performance integrated silicon-based passive components with high density are required to reduce the overall cost and bulkiness of the systems. This paper presents the development of high-density ultra-thin 3D capacitors in silicon, one of the important passive components exploited in approximately all the circuits for SiP, 3D-integration and flexible systems. The 3D structure is achieved by using deep reactive ion etching (DRIE) process. The substrate and the polysilicon act as the two electrode plates with silicon dioxide as the dielectric. Two designs with different pitches are investigated with successful back-grinding of the substrate to 50$\mu$ m thin and 22$\mu$ m ultra-thin singulated capacitors. Capacitive densities of 36.25 nF/mm 2 and 28.75 nF/mm 2 over a frequency bandwidth of 100 KHz are presented. The reduced thickness and flexible nature of these ultra-thin capacitors (

This paper reports on the status of a comprehensive ten-year research and development effort towards Hybrid System-in-Foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion attached on or laminated in a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity or form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on- and off-chip implementation of sensor, actuator, microwave and energy supply components are discussed.

Ultrathin chip fabrication is an enabler of high-performance hybrid systems-in-foil (HySiF) for flexible electronics as well as 3D IC's. Minimum chip thickness, exact thickness control, uniformity and reproducibility as well as smoothness of chip surfaces and edges are important requirements in both applications. Most commonly, thinning is arranged at wafer level prior to chip singulation, which is classified as a subtractive method. In contrast, an additive thin-chip technology called ChipFilm™ is presented here, meeting all those requirements. It is shown that by using ChipFilm™ both wafer-level and chip-level thinning are feasible.

Various aspects of ultra-thin chip technology for flexible electronics are presented and discussed, including ultra-thin-chip fabrication, mechanical and electrical characterization, as well as chip assembly and imbedding. A stress sensor based on a stack of two ultra-thin, flexible CMOS chips indicates the particular advantages of the Chipfilm™ process technology, which is subject of this paper, when compared to other kinds of thin-chip fabrication.

Here, we present a flexible sensor based on a stack of two ultra-thin IC-chips, exploiting the excellent chip thickness control in Chipfilm™ technology. The sensor consists of an almost stress-compensated bottom chip and a stress-sensitive top chip that are in good mechanical and thermal contact. Moreover, for the first time, we demonstrate that the chip thickness can be reduced to 10 μm, with the bulk Si body measuring only 7 μm, thus allowing for flexible chipstacks measuring only 20 μm in height. Furthermore, we demonstrate a self-aligned Through-Silicon Via (TSV) process in Chipfilm™ enabling 3D integration of such ultra-thin flexible chip pairs.

Various aspects of ultra-thin chip technology for flexible electronics based on Chipfilm™ technology are presented and discussed, including ultra-thin-chip fabrication, mechanical and electrical characterization, as well as chip assembly and imbedding.

Here, we present a new concept for enabling the formation of TSVs in ultra-thin chips fabricated by using the ChipfilmTM technology. In this technology a buried cavity is created underneath a Si-membrane which is attached to the substrate by vertical silicon anchors. By applying thermal oxidation, the side walls of these anchors and the narrow cavity are passivated. Due to the high selectivity of the silicon via etching process the oxidized silicon anchors and chip backside can be exploited for creating self-aligned TSVs. Accordingly, a seamless oxide isolation at the chip backside and inside the TSVs is provided.

Ultra-thin silicon (Si) chips fabricated using the recently developed ChipfilmTM technology feature three distinct manufacturing issues, which are discussed in this paper. In Chipfilm™ technology a thin Si membrane is firmly attached to a conventional bulk Si wafer by vertical Si micro-anchors which, however, in the end are controllably fractured to make the thin chips detachable. The associated mechanical stability window is widened by adjusting the arrangement of the micro-anchors, so that chip detachment yields exceeding 99% are achieved. Another not yet reported issue relates to the process temperature and temperature uniformity within the membrane areas, which are thermally connected to the bulk substrate only by the anchors and at the chip edges during processing. Using rapid thermal oxidation and the local oxide thickness as a temperature monitor an on-chip oxide thickness variation of ±3 % is determined. Finally, the inherent deformation (warpage) of free-standing ultra-thin chips due to internal stresses is analyzed and their surface height variation is reduced to only ±4 μm using stress compensation techniques.

This paper reports about the development of a low-cost, CMOS compatible process technology to create thermally insulated pixel regions for integrated microbolometers. The enabling technology is based on a modified sintered porous silicon (sPS) technique. An array of 280 × 240 thermally isolated pixels with lateral dimensions of 30 × 30 μm2 and epitaxial silicon (Si) thickness down to 500 nm is presented. In the final design the pixel is suspended by silicon dioxide (SiO 2 ) arms. The design and fabrication process is described and mechanical deformation properties subtracted from profilometer images are presented.

Background: Obesity is a serious and chronic medical condition associated with a wide range of lifethreatening disease and resulting in enormous financial costs being born by health-care systems and the community itself. In an effort to reverse the current global epidemic of overweight and obesity, strategies to encourage healthy eating have been promoted in many countries. In order to develop appropriate and effective obesity prevention strategies for young women it is important to understand the barriers they perceive in attempting to reduce their weight and to examine perceptions of a range of personal, social and environmental barriers to healthy eating. Objectives: To identify the range of perceived personal, social and environmental barriers to healthy eating for weight reduction among young Saudi overweight and obese women and to determine how these barriers varied by socio-demographic status and socio-economic status. Design: Cross sectional descriptive study. Method: 302 patients were requested to fill in a questionnaire. It identified personal data, body weight and barriers for healthy diet among adult overweight and obese women. Results: Questionnaires were filled in by 302 overweight and obese patients. We examined 10 barriers. The main barriers reported by women related to a need of special prepared, separated food from family (62.3%), lack of information, skills to plan and prepare a healthy diet (61.2%), easy availability of fast food (56%), lack of time to prepare healthy food because of family commitments (55%), lack of motivation to eat healthy diet accounted for 56.6%, cost of healthy food accounting for 48%, lack of family, friends encouragement and support (49.4%) and 42.7% of ladies consider overeating was related to social stressors, as important barriers. Conclusion: Overall, the study showed a descriptive analysis to the perceived barriers to healthy diet among adult overweight and obese women. Such barriers can be overcome by development of individualized healthy diet programs and implementation of behavioral and social approaches for encouragement of a healthy diet.

A new additive ultra-thin chip fabrication process is presented, utilizing an array of vertical anchors that mechanically connect silicon membrane chips to a standard silicon wafer. The process is demonstrated down to 8 µm silicon chip thickness, with a chip thickness control better than ±0.2 µm and a surface topography with average roughness < 7 nm. Such pre-processed wafers can be used for CMOS manufacturing like any conventional silicon substrate. A wide process window with yield figures exceeding 99% is achieved by proper management of the built-in and externally applied stress on the anchors. The excellent mechanical flexibility and stability of these ultra-thin chips make them particularly suitable for system-in-foil applications.

For astronomical applications, different types of step-index all-silica fibers with high-transparency in the whole spectral region from UV (300 nm) to NIR (1100 nm) will be introduced. The light-guiding core-material consists of high-purity silica, especially with low or medium OH-content. In UV region, the losses are mainly influenced by Rayleigh scattering, while the losses in the IR region are limited by traces of OH-groups (in the order of approx. 2 ppm) and fundamental vibration-bands. Due to processing, typical UV-defects below 280 nm can be suppressed significantly within fibers with medium or low OH-content. Especially, one fiber-type with low-OH content in the core possess high resistance against UV radiation in the DUV-region down to 200 nm, which is comparable to high-OH all-silica fibers specially developed for UV-application below 250 nm. In addition, a medium-OH will be presented. The properties of these new fibers in respect to basic attenuation and spectral damage in the UV-region will be discussed, in comparison to high-OH fibers, based on the same measurement-technique. In addition, first results on focal ratio degradation (FRD) and additional loss related to higher propagation angles will be shown, in comparison to standard high-OH fibers.