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We propose a new and fast method for monitoring contact hole roughness (CHR), which can be a major yield-loss factor for advanced SRAMs. The method, defect-review scanning electron microscopy (SEM) image processing, can monitor CHR 100 times faster than the conventional method by critical dimension (CD)-SEM. The speed can facilitate faster identification of process countermeasures by, for example, making detailed monitoring of CHR variation within a wafer practicable. Results for CHR obtained by both new and conventional methods show similar trends for differences in process conditions. Also, we experimentally confirmed the new method's measuring variation of the rate of deformed contact holes. Through evaluation by the new method, we demonstrate that the standby electric current of advanced SRAM depends not only on overlay error but also on CHR. We believe that the new method will be very useful in the evaluation of process countermeasures and their stability. Index Terms--Electron beams, inspection, integrated circuit manufacture, logic devices, SRAM chips.

We examine a technique for enhancing the voltage contrast (VC) of a failure analysis (FA) tool, defect review scanning electron microscope (DR-SEM). For an SRAM, we demonstrate a dependence of gate-leak VC on the relative angle (RA) between the direction of beam scanning by the FA tool and the lengthwise direction of the gate electrode. Experimental results show that better VC results are obtained when RA is zero, in other words, a beam's scan-line is parallel with the SRAM gate. We propose a simple qualitative resistor-capacitor model to explain this phenomenon. With the help of this VC enhancement technique of the FA tool, we could tune the electron beam inspection (EBI) recipe to an appropriate condition quicker. The cycle time of EBI recipe tuning was shortened from five to two days. As a result, correct EBI evaluation results of countermeasure experiments led us to a yield enhancement solution within a shorter period of time. Index Terms--Dielectric breakdown, electron beams, failure analysis (FA), inspection, integrated circuit (IC) manufacture, leak detection, logic devices, SRAM chips, voltage measurement.

The authors propose a new accurate yield prediction method for system-LSI embedded memories to improve the productivity of chips. Their new method is based on the failure-related yield prediction method in which failure bits in memory are tested to see whether they are repairable or not by using built-in redundancies. The important concept of the new method is called 'repairable matrix' (RM). In RM, r[m.sub.ij] = 1 means that i row redundancy sets and j column redundancy sets are needed for repair, where r[m.sub.ij] is an element of the matrix. Here, RM can indicate all the candidate combinations of the number of row and column redundancy sets for repair. The new yield prediction method using RM solves two problems, 'asymmetric repair' and 'link set.' These have a significant effect on accurate yield prediction but have not yet been approached by conventional analytical methods. The calculation of yield by the new method is demonstrated in two kinds of advanced memory devices that have different design rules, failure situations, and redundancy designs. The calculated results are consistent with the actual yield. On average, the difference in accuracy between the new method and conventional analytical methods is about 5%. Index Terms--Embedded memory, failure, redundancy, semiconductor manufacturing, yield prediction.

In this paper, we demonstrate a new method of improving the defect controllability of grainy metal layers, for example, Hot-Al-Cu wiring, by enhancing the practical sensitivity of in-line inspectors. The problem in increasing practical sensitivity is the nuisance counts caused by grain boundaries, which do not cause electrical failures. We propose a method of decreasing the signal from the grain boundaries. On the grayscale images taken by pattern matching inspectors, grain boundaries are observed as gray on Hot-Al-Cu wiring, which is observed as white. If the illumination brightness is increased, the gray level of the grain boundaries becomes higher and saturates at the upper limit of grayscale, i.e., white. On the other hand, the gray level of the wiring stays white. Thus the signal, the grayscale difference between the grain boundaires and the wiring, can be decreased to almost zero. We call this phenomenon the 'saturation effect.' Our experimental results prove that the saturation effect due to illumination brightness optimization successfully cancels the nuisance counts caused by grain boundaries. The practical sensitivity limit is enhanced from 0.8 to 0.4 [micro]m. This solution will greatly improve the defect controllability of grainy metal layers. Index Terms--Grayscale, in-line inspection, pattern matching inspector, patterned inspection, semiconductor manufacturing.