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A new method for fluoroscopic tracking of a proximal bone fragment in femoral fracture reduction is presented. The proposed method combines 2-D and 3-D image registration from single-view fluoroscopy with tracking of the head center position of the proximal femoral fragment to improve the accuracy of fluoroscopic registration without the need for repeated manual adjustment of the C-arm as required in stereo-view registrations. Kinematic knowledge of the hip joint, which has a positional correspondence with the femoral head center and the pelvis acetabular center, allows the position of the femoral fragment to be determined from pelvis tracking. The stability of the proposed method with respect to fluoroscopic image noise and the desired continuity of the fracture reduction operation is demonstrated, and the accuracy of tracking is shown to be superior to that achievable by single-view image registration, particularly in depth translation. Index Terms--Fluoroscopic bone fragment tracking, fracture reduction, kinematic knowledge of the hip joint, motion constraint.

A new study investigates the high-frequency AC characteristics of 1.5nm gate oxide CMOS.

An RF power Si-MOSFET design method for low voltage operation and high power added efficiency, is proposed.

CMOS salicide processes are examined.

A high performance silicided silicon-sidewall source and drain structure (S4D) was presented that surmounts the limitations of conventional lightly doped drain and solid-phase diffused drain structures. With S4D, the source and drain resistance is diminished by placing the silicide layer near the gate electrode and increasingly doping the silicon sidewall. Furthermore, shallow extensions with very high doping can be expected from the S4D structure.

A 0.15-micron radio frequency (RF) complementary metal-oxide semiconductor (CMOS) technology that is compatible with logic CMOS for low-voltage operation is presented. Manufacturibility of this technology is excellent since the fabrication process is the same as the high-speed logic. Excellent high-frequency properties of small geometry silicon metal oxide semiconductor field effect transistors with low-power supply voltage are demonstrated.

Silicon metal oxide semiconductor field effect transistors (MOSFETs) with a counter-doped ultrathin epitaxial channel deposited by low-temperature UHV-CVD, which allows the channel region to be doped with high precision, are presented. It is easy to adjust the threshold voltage of the p-MOSFETs since boron concentration and epitaxial layer thickness can be selected independently. Results demonstrate that epitaxial channel technology will be useful in the production of MOSFETs having gate lengths of 0.15 micron and below.

The electrical characteristics and relation between the process conditions of low-temperature epitaxial growth of n-metal oxide semiconductor field effect transistors (MOSFETs) were examined to improve the performance of ultrashallow undoped epitaxial channel n-MOSFETs. The relationship between G(sub m) and the surface density of oxygen at the epitaxial silicon/silicon substrate was determined. Results indicate that epitaxial silicon channel MOSFETs are useful for future high-speed ULSI devices.

Research using two-dimensional simulation techniques shows that S4D metal oxide semiconductor field effect transistors exhibit reliable hot carrier characteristics. High drain current and well-suppressed short channel effects are observed. Threshold shift and charge pumping current effects are notably more when compared to LDD structures. Lateral component profiles for electric fields in both devices are illustrated.

The performance of 1.5 nm direct-tunneling gate oxide n-MOSFETs improves with a reduced gate length of about 0.1 micro-m. The gate leakage current declines while the drain current increases with the reduction of the gate length to provide enhanced transistor operations. The ultra-thin gate oxide with deep source and drain junctions affect high values of transconductance and current drive at room temperature. There is an improvement in the hot-carrier reliability with the reduction in gate thickness. The importance of a high-capacitance gate insulator in Si devices is discussed.

The fabrication a 40-nanometer (nm) gate length n-MOSFET involves the use of a resist thinning technique and a solid phase diffusion technique. The n-MOSFET's have ultra-shallow source and drain junctions, and operate normally at room temperature. A reduction in gate length to around 40 nm causes the impact ionization rate to increases moderately. The problem of degradation due to hot carriers is negligible and the performance is reliable for Vd < or = 1.5 volts.

Substrate current and impact ionization rate depend on impurity concentration in N-MOSFET. Both these hot carrier characteristics increase with increasing substrate impurity concentration in long channel devices and decrease in short channel devices. Reduction in gate oxide thickness decreases off-leakage current. Increase in substrate impurity concentrations decreases the degradation of drain currents.

Examination of the increase in sheet resistance in TiSi2-polysilicon films reveals that it occurs during the narrowing of the line width, with three different regions defining the correlation between sheet resistance and line width. Large inter-grain layers with low silicide levels cause the increase in sheet resistance. NiSi films, unlike TiSi2 films, do not display an increase in sheet resistance.

Numerical simulations of the electrical properties of various devices evaluates the possibility constructing a sub-0.1 micrometer metal oxide semi-conductor field effect transistor (MOSFET). The simulations scale the supply voltage and oxide thickness limit of the MOSFET for ultra-short gate lengths to maintain them at constant values. Several limitations for developing a thin, intrinsic, epitaxial silicon layer on a highly doped substrate are formulated.

Studies on P-MOSFETs with a solid phase diffused drain (SPDD) structure reveal that the SPDD is valid for MOSFETs operating in the sub 0.1 micron domain. The SPDD P-MOSFETs have an ultra-shallow high-concentration drain configuration which improves short channel effects without a consequent resistance increase. The MOSFET is very reliable with respect to hot-carrier operations.

Adynamic bone disease in HD patients is characterized by skeletal resistance to parathyroid hormone (PTH) or suppression of PTH release, leading to a downregulated bone turnover and bone fracture. Hence, we examined the efficacy of weekly teriparatide for HD patients with low PTH indicating adynamic bone disease without a history of parathyroidectomy. Fifteen HD patients with low PTH were recruited in this prospective observational study. Of them, 10 received teriparatide for 12 months and five nontreated patients were enrolled as control. Primary outcomes were defined as the changes in bone mineral density and bone turnover markers. Bone mineral density at the lumbar spine increased by 3.7% and 2.5% at 6 and 12 months, respectively, and bone formation markers increased, while bone resorption markers did not change in the teriparatide group. At 12 months after teriparatide administration, endogenous PTH was secreted followed by the recovery of low bone turnover. 40% of patients in the teriparatide group dropped out due to adverse events and the most common adverse event was transient hypotension. This study suggests that weekly teriparatide for HD patients with low PTH in the absence of parathyroidectomy accelerates bone formation and bone turnover, leading to increased trabecular bone mass and secretion of endogenous PTH. [ABSTRACT FROM AUTHOR]