Search

Your search keyword '"Sahu, Anubhav"' showing total 105 results
Start Over Author "Sahu, Anubhav"
105 results on '"Sahu, Anubhav"'

4. Implementation of Energy Efficient Single Flux Quantum (eSFQ) Digital Circuits with sub-aJ/bit Operation

Author

Volkmann, Mark Hans, Sahu, Anubhav, Fourie, Coenrad Johan, and Mukhanov, Oleg A.

Subjects
Condensed Matter - Superconductivity
Abstract

We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing., Comment: 28 Pages

Published
2012
Full Text
View/download PDF

12. 64-GHz Operation of the Pseudorandom Binary Sequence Generator Using the Dual RSFQ/ERSFQ Standard Cell Library

Author

Inamdar, Amol, Ravi, Jushya, Habib, Mustapha, Meher, Sukanya S., Sahu, Anubhav, and Gupta, Deepnarayan

Abstract

A pseudorandom binary sequence of 7-bit word length (PRBS-7) generator has been designed as a low complexity circuit to validate the dual RSFQ/ERSFQ standard cell library, the circuit simulation methodology using process corners and Monte-Carlo statistical variations, as well as the digital design methodology using Verilog simulations with load-dependent timing back-annotation. The PRBS-7 design was optimized across multiple process corners with Monte-Carlo circuit simulations by incorporating statistical variations of the process parameters. To validate the digital design flow, the PRBS-7 was simulated using the Verilog behavioral descriptions of library cells. Using Liberty files for different global bias current (XI) process corners, the margins obtained from digital simulation were compared with circuit simulations. A 5 mm × 5 mm chip, incorporating both the RSFQ and ERSFQ variant of the PRBS-7, was fabricated in the MIT-LL 100 μA/μm2 SFQ5ee fab node. The RSFQ variant of the PRBS-7 has been successfully tested up to 64.77-GHz clock frequency, and the ERSFQ variant up to 45.72-GHz clock frequency. In addition, we have analyzed the model-to-hardware correlation for RSFQ PRBS-7 for different clock frequencies. The simulations account for two process parameters, critical current density (Jc), and sheet resistance (Rs).

Published
2023
Full Text
View/download PDF

20. Look-up table for superconductor digital-RF predistorter

Author

Filippov, Timur V., Sahu, Anubhav, Kirichenko, Alex F., and Gupta, Deepnarayan

Subjects
Integrated circuit fabrication -- Analysis, Power amplifiers -- Design and construction, Integrated circuit fabrication, Business, Electronics, Electronics and electrical industries
Abstract

A high-speed pipelined superconductor look-up table comprising of address decoder and a memory matrix with throughput above 10 GHz, developed to generate programmable predistortion functions for direct linearization of radio frequency (RF) power amplifiers is described.

Published
2007

21. Digital encoder for RF transmit waveform synthesizer

Author

Inamdar, Amol, Gupta, Deepnarayan, Sarwana, Saad, Sahu, Anubhav, and Kadin, Alan M.

Subjects
Waveforms -- Analysis, Digital-to-analog converters -- Design and construction, Encoders -- Design and construction, Business, Electronics, Electronics and electrical industries
Abstract

The design of an encoder for conversion of a nyquist-rate N-bit digital word into a high frequency stream of single-bit data which would enable a novel architecture for a digital waveform synthesizer is described.

Published
2007

22. Decimation filter with improved DC biasing and data transfer

Author

Inamdar, Amol, Sahu, Anubhav, and Semenov, Vasili

Subjects
Strip transmission lines -- Usage, Electric filters -- Design and construction, Superconductors -- Electric properties, Superconductors -- Usage, Business, Electronics, Electronics and electrical industries
Abstract

Two new techniques related to decimation filters which deals with DC biasing scheme which saves space during the connection of separate power lines after the circuit is debugged and the selective use of micro-strip lines is described.

Published
2007

23. Quarter-rate superconducting modulator for improved high resolution analog-to-digital converter

Author

Inamdar, Amol, Rylov, Sergey, Sahu, Anubhav, Sarwana, Saad, and Gupta, Deepnarayan

Subjects
Analog to digital converters -- Design and construction, Phase modulation -- Analysis, Superconductive devices -- Design and construction, Business, Electronics, Electronics and electrical industries
Abstract

The design of a new oversampled analog-to-digital converter (ADC) based on the phase modulation-demodulation (PMD) architecture which comprises of a quarter-rate quantizer tested at an input frequency of 81.92 GHz is presented.

Published
2007

24. Superconducting high-resolution low-pass analog-to-digital converters

Author

Vernik, Igor K., Kirichenko, Dmitri E., Filippov, Timur V., Talalaevskii, Andrei, Sahu, Anubhav, Inamdar, Amol, Kirichenko, Alex F., Gupta, Deepnarayan, and Mukhanov, Oleg A.

Subjects
Analog to digital converters -- Design and construction, Integrated circuit fabrication -- Analysis, Circuit design -- Analysis, Integrated circuit fabrication, Circuit designer, Integrated circuit design, Business, Electronics, Electronics and electrical industries
Abstract

A high-resolution, dynamically programmable analog-to-digital converter (ADC) which uses the phase modulation-demodulation low-pass architecture and on-chip digital filtering for radar and communications applications is presented.

Published
2007

25. Digital channeling radio frequency receiver

Author

Gupta, Deepnarayan, Filippov, Timur V., Kirichenko, Alexander F., Kirichenko, Dmitri E., Vernik, Igor V., Sahu, Anubhav, Sarwana, Saad, Shevchenko, Pavel, Talalaevskii, Andrei, and Mukhanov, Oleg A.

Subjects
Radio waves -- Analysis, Josephson junction -- Analysis, Electric filters, Bandpass -- Design and construction, Business, Electronics, Electronics and electrical industries
Abstract

A digital channelizer circuit, containing more than 10,000 Josephson junctions integrated with lowpass and bandpass ADCs which demonstrate a set of single-chip digital RF receivers is presented.

Published
2007

26. Superconductor components for direct digital synthesizer

Author

Mukhanov, Oleg, Inamdar, Amol, Filippov, Timur, Sahu, Anubhav, Sarwana, Saad, and Semenov, Vasili

Subjects
Digital-to-analog converters -- Design and construction, Superconductors -- Electric properties, Business, Electronics, Electronics and electrical industries
Abstract

The development of a direct digital synthesizer (DDS) based on a novel digital-to-analog converter (DAC) technology capable of directly generating wideband signals at RF with large signal-to-noise ratio (SNR) and spur-free dynamic range (SFDR) is reported.

Published
2007

27. Characterization of HYPRES' 4.5 kA/cm(super 2) & 8 kA/cm(super 2) Nb/AlO(sub x)/Nb fabrication processes

Author

Yohannes, Daniel, Sarwana, Saad, Tolpygo, Sergey K., Sahu, Anubhav, Polyakov, Yuri A., and Semenov, Vasili K.

Subjects
Aluminum oxide -- Electric properties, Integrated circuit fabrication -- Methods, Josephson junction -- Design and construction, Integrated circuit fabrication, Business, Electronics, Electronics and electrical industries
Abstract

HYPRES has developed new fabrication processes for higher critical current density Josephson junctions (JJ's). The critical current speeds and shunt resistance uniformity along with the effects of junction shape are described.

Published
2005

28. Fast RSFQ and ERSFQ Parallel Counters

Author

Eren Celik, Mustafa, primary, Filippov, Timur V., additional, Sahu, Anubhav, additional, Kirichenko, Dmitri E., additional, Sarwana, Saad M., additional, Lehmann, A. Erik, additional, and Gupta, Deepnarayan, additional

Published
2020
Full Text
View/download PDF

32. Fast RSFQ and ERSFQ Parallel Counters

Author

Celik, M. Eren, primary, Filippov, Timur V., additional, Sahu, Anubhav, additional, Kirichenko, Dmitri E., additional, Sarwana, Saad M., additional, Lehmann, A. Erik, additional, and Gupta, Deepnarayan, additional

Published
2019
Full Text
View/download PDF

41. Design and Evaluation of Flash ADC

Author

Inamdar, Amol, primary, Sahu, Anubhav, additional, Ren, Jie, additional, Setoodeh, Sormeh, additional, Mansour, Raafat, additional, and Gupta, Deepnarayan, additional

Published
2015
Full Text
View/download PDF

45. Look-Up Table for Superconductor Digital-RF Predistorter

Author

HYPRES INC ELMSFORD NY, Filippov, Timur V., Sahu, Anubhav, Kirichenko, Alex F., Gupta, Deepnarayan, HYPRES INC ELMSFORD NY, Filippov, Timur V., Sahu, Anubhav, Kirichenko, Alex F., and Gupta, Deepnarayan

Abstract

We have developed a high-speed pipelined superconductor look-up table to generate programmable predistortion functions for direct linearization of radio frequency "RF" power amplifiers. The look-up table comprises an address decoder and a memory matrix with throughput above 10 GHz. The decoder performs code-matching of each input word and its conversion into a row address of the memory matrix. We discuss different possible implementations of the address decoder, including a preferred one for integrated circuit implementation. The memory matrix consists of RS flip-flops with nondestructive readout connected in series for slow-speed contents writing. Each row of the memory matrix contains a number, which can be read out by signal from the decoder. We present the design and the results of experimental evaluation of the look-up table and its components., Published in the Jnl. of IEEE Transactions on Applied Superconductivity v17, n2, p561-564, Jun 2007. Sponsored in part by CERDEC SBIR contracts.

Published
2007

46. Quarter-Rate Superconducting Modulator for Improved High Resolution Analog-to-Digital Converter

Author

HYPRES INC ELMSFORD NY, Inamdar, Amol, Rylov, Sergey, Sahu, Anubhav, Sarwana, Saad, Gupta, Deepnarayan, HYPRES INC ELMSFORD NY, Inamdar, Amol, Rylov, Sergey, Sahu, Anubhav, Sarwana, Saad, and Gupta, Deepnarayan

Abstract

We describe the design of a new oversampled analog-to-digital converter (ADC) based on phase modulation-demodulation (PMD) architecture. In a PMD ADC, the analog input signal modulates the phase of a periodic stream of fluxons applied to a modulator circuit for subsequent demodulation in a clocked synchronizer circuit to produce a digital code. The new modulator provides a way to quadruple the average fluxon transport rate, and hence the input dynamic range, by replacing the single junction interferometer with a high-speed symmetric divide-by-4 circuit. The divider acts as a 1:4 asynchronous demultiplexer which distributes incoming fluxons amongst its four quarter-rate outputs. This four-fold rate reduction, at the modulator output, allows one to increase the ADC maximum input slew rate to 2 fluxons per clock period, achieving 2 additional bits of resolution at the same sampling clock frequency. We have designed and fabricated a quarter-rate ADC front-end and present low frequency test results for the same. The ADC comprises a quarter-rate quantizer which has been successfully tested at an input frequency of 81.92 GHz.

Published
2006

50. Components for Superconductor Digital-RF Predistorter.

Author

Sahu, Anubhav, Filippov, Timur V., and Gupta, Deepnarayan

Subjects
*SUPERCONDUCTORS, *ELECTRIC distortion, *RADIO frequency, *POWER amplifiers, *DIFFERENTIAL amplifiers, *DECODERS (Electronics)
Abstract

HYPRES is developing a superconductor digital-RF predistorter for direct linearization of radio frequency (RF) power amplifiers. The predistorter utilizes proportional (P), squared integral (I) and differential (D) corrections. We report progress in the proportional component implementation. We designed, fabricated and tested a 4-to-16 decoder, a 16-to-6 memory matrix and a test pattern generator integrated on a 10 mm x 10 mm chip. We also designed a pipelined differentiator, the critical element of the differential component, and its combination with the decoder. The correct operation of a resettable counter to implement the integral predistorter function is reported. The design issues of the complete superconductor PID predistorter are discussed in brief. [ABSTRACT FROM AUTHOR]

Published
2009
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results