Search

Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), and Buffer (BUFG). The system's highest frequency is 107.979 MHz, achieving different throughputs for cryptographic hash functions. Specifically, it performs a throughput of 5.183 Gbps for SHA3-224, 4.895 Gbps for SHA3-256, 3.743 Gbps for SHA3-384, and 2.591 Gbps for SHA3-512. ABSTRAK: Menggunakan SHA-3 pada peranti FPGA memerlukan peruntukan sumber yang ketara, walaupun daya pengeluaran yang terhasil adalah terhad. Untuk menangani isu ini, kajian ini menggunakan modul DSP48 yang disertakan pada Xilinx FPGA dan melaksanakan metodologi saluran paip lapan peringkat untuk meminimumkan kependaman. Reka bentuk pelaksanaan terdiri daripada laluan data dan modul pengawal, menggunakan siri FPGA Xilinx Artix-7-100T sebagai perkakasan. Kaedah ini menggunakan sumber FPGA seperti Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), dan Penampan (BUFG). Kekerapan tertinggi sistem ialah 107.979 MHz, dan ia mencapai daya pemprosesan yang berbeza untuk fungsi cincang kriptografi yang berbeza. Secara khususnya, ia mencapai daya pemprosesan 5.183 Gbps untuk SHA3-224, 4.895 Gbps untuk SHA3-256, 3.743 Gbps untuk SHA3-384 dan 2.591 Gbps untuk SHA3-512.

With the standardization of NIST post-quantum cryptographic (PQC) schemes, optimizing these PQC schemes across various platforms presents significant research value. While most existing software implementation efforts have concentrated on ARM platforms, research on PQC implementations utilizing various RISC-V instruction set architectures (ISAs) remains limited. In light of this gap, this paper proposes comprehensive and efficient optimizations of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V}. We thoroughly optimize these implementations for dual-issue CPUs, believing that our work on various RISC-V ISAs will provide valuable insights for future PQC deployments. Specifically, for Keccak, we revisit a range of optimization techniques, including bit interleaving, lane complementing, in-place processing, and hybrid vector/scalar implementations. We construct an optimal combination of methods aimed at achieving peak performance on dual-issue CPUs for various RISC-V ISAs. For the NTT implementations of Kyber and Dilithium, we deliver optimized solutions based on Plantard and Montgomery arithmetic for diverse RISC-V ISAs, incorporating extensive dual-issue enhancements. Additionally, we improve the signed Plantard multiplication algorithm proposed by Akoi et al. Ultimately, our testing demonstrates that our implementations of Keccak and NTT across various ISAs achieve new performance records. More importantly, they significantly enrich the PQC software ecosystem for RISC-V.

SHA-3, the latest hash standard from NIST, is utilized by numerous cryptographic algorithms to handle sensitive information. Consequently, SHA-3 has become a prime target for side-channel attacks, with numerous studies demonstrating successful breaches in unprotected implementations. Masking, a countermeasure capable of providing theoretical security, has been explored in various studies to protect SHA-3. However, masking for hardware implementations may significantly increase area costs and introduce additional delays, substantially impacting the speed and area of higher-level algorithms. In particular, current low-latency first-order masked SHA-3 hardware implementations require more than four times the area of unprotected implementations. To date, the specific structure of SHA-3 has not been thoroughly analyzed for exploitation in the context of masking design, leading to difficulties in minimizing the associated area costs using existing methods. We bridge this gap by conducting detailed leakage path and data dependency analyses on two-share masked SHA-3 implementations. Based on these analyses, we propose a compact and low-latency first-order SHA-3 masked hardware implementation, requiring only three times the area of unprotected implementations and almost no fresh random number demand. We also present a complete theoretical security proof for the proposed implementation in the glitch+register-transition-robust probing model. Additionally, we conduct leakage detection experiments using PROLEAD, TVLA and VerMI to complement the theoretical evidence. Compared to state-of-theart designs, our implementation achieves a 28% reduction in area consumption. Our design can be integrated into first-order implementations of higher-level cryptographic algorithms, contributing to a reduction in overall area costs.

This article analyzes the dynamic power losses generated by various hardware implementations of the BLAKE3 hash function. Estimations of the parameters were based on the results of post-route simulations of designs implemented in Xilinx Spartan-7 FPGAs. The algorithm was tested in various hardware organizations: based on a standard iterative architecture with one round instance in the programmable array, various derived versions with pipeline processing were elaborated, which ultimately led to a set of 6 architectural variants of the cipher, from the iterative case (without pipeline) to one with maximum of 6 pipeline stages. Moreover, the results obtained for the iterative architecture were compared with analogous implementations of the BLAKE2 (direct predecessor) and KECCAK (the foundation of the current SHA-3 standard) algorithms. This case study illustrates the differences (or lack thereof) in the power requirements of these three hash functions when they are implemented on an FPGA platform, and illustrate the significant savings that can be achieved by introducing pipeline to the processing of the BLAKE round.

Competitions are widely viewed as the safest way to select cryptographic algorithms. This paper surveys procedures that have been used in cryptographic competitions, and analyzes the extent to which those procedures reduce security risks. [ABSTRACT FROM AUTHOR]

This article analyzes the dynamic power losses generated by various hardware implementations of the BLAKE3 hash function. Estimations of the parameters were based on the results of post-route simulations of designs implemented in Xilinx Spartan-7 FPGAs. The algorithm was tested in various hardware organizations: based on a standard iterative architecture with one round instance in the programmable array, various derived versions with pipeline processing were elaborated, which ultimately led to a set of 6 architectural variants of the cipher, from the iterative case (without pipeline) to one with maximum of 6 pipeline stages. Moreover, the results obtained for the iterative architecture were compared with analogous implementations of the BLAKE2 (direct predecessor) and KECCAK (the foundation of the current SHA-3 standard) algorithms. This case study illustrates the differences (or lack thereof) in the power requirements of these three hash functions when they are implemented on an FPGA platform, and illustrate the significant savings that can be achieved by introducing pipeline to the processing of the BLAKE round. [ABSTRACT FROM AUTHOR]

This paper conducts an extensive comparative study of state-of-the-art solutions for implementing the SHA-3 hash function. SHA-3, a pivotal component in modern cryptography, has spawned numerous implementations across diverse platforms and technologies. This research aims to provide valuable insights into selecting and optimizing Keccak SHA-3 implementations. Our study encompasses an in-depth analysis of hardware, software, and software–hardware (hybrid) solutions. We assess the strengths, weaknesses, and performance metrics of each approach. Critical factors, including computational efficiency, scalability, and flexibility, are evaluated across different use cases. We investigate how each implementation performs in terms of speed and resource utilization. This research aims to improve the knowledge of cryptographic systems, aiding in the informed design and deployment of efficient cryptographic solutions. By providing a comprehensive overview of SHA-3 implementations, this study offers a clear understanding of the available options and equips professionals and researchers with the necessary insights to make informed decisions in their cryptographic endeavors. [ABSTRACT FROM AUTHOR]

Forensic in cloud computing is an advancement of evolutionary modern forensic science that protects against cyber criminals. Single centralize point compilation and storage of data, however, overcome the authenticity of digital evidence. In order to address this serious issue, this article suggests a evolutionary modern algorithm automated forensic platform leveraging infrastructure as a cloud service (IaaS) based on Blockchain concept. This proposed forensic structural design, evidence collection of evidence and stored on a blockchain which is circulated around several peer blocks. Secure Block Verification Mechanism (SBVM) is proposed to Safeguarding the device from unauthorised users. Using the Backtracking Search Optimization Algorithm search optimization algorithm for strengthening of the cloud environment, secret keys are optimally generated. On the bases of level of confidentiality, all data is stored and encrypted at cloud authentication server. Confidentiality-based Algebraically Homomorphic Cryptosystems learning is presented with a fast-forwarding algorithm for encryption. A block in the SDN controller is created for every data and information is stored in the cloud service provider and the history is recorded as metadata data about data. A hash based tree is constructed in each block by Secure Hash Algorithm version - 3 of 512 bits. By implementing graph theory-based graph neural networks in Smart Contracts, our framework enables users to track their data (GNNSC). Finally, the construction of a evidence graph using blockchain data enables evidence analysis. Experiments was carried out in a Python programming and blockchain integrated cloud environment with network simulator-3.30 (for Software Defined Network). As part of result our newly designed forensic architecture using blochchain (FAuB) good results in terms of evidence response time, insertion times of cloud evidence, verification time of evidence, computational overhead of evidence, hashes calculation time, keys generations times of evidence, evidence encryption time, evidence decryptions time, and total overall change rate of evidence, according to a comprehensive comparative study. [ABSTRACT FROM AUTHOR]

Information is transmitted between multiple insecure routing hops in text, image, video, and audio. Thus, this multi-hop digital data transfer makes secure transmission with confidentiality and integrity imperative. This protection of the transmitted data can be achieved via hashing algorithms. Furthermore, data integrity must be ensured, which is feasible using hashing algorithms. The advanced cryptographic Secure Hashing Algorithm 3 (SHA-3) is not sensitive to a cryptanalysis attack and is widely preferred due to its long-term security in various applications. However, due to the ever-increasing size of the data to be transmitted, an effective improvement is required to fulfill real-time computations with multiple types of optimization. The use of FPGAs is the ideal mechanism to improve algorithm performance and other metrics, such as throughput (Gbps), frequency (MHz), efficiency (Mbps/slices), reduction of area (slices), and power consumption. Providing upgraded computer architectures for SHA-3 is an active area of research, with continuous performance improvements. In this article, we have focused on enhancing the hardware performance metrics of throughput and efficiency by reducing the area cost of the SHA-3 for all output size lengths (224, 256, 384, and 512 bits). Our approach introduces a novel architectural design based on pipelining, which is combined with a simplified format for the round constant (RC) generator in the Iota (ι) step only consisting of 7 bits rather than the standard 64 bits. By reducing hardware resource utilization in the area and minimizing the amount of computation required at the Iota (ι) step, our design achieves the highest levels of throughput and efficiency. Through extensive experimentation, we have demonstrated the remarkable performance of our approach. Our results showcase an impressive throughput rate of 22.94 Gbps and an efficiency rate of 19.95 Mbps/slices. Our work contributes to advancing computer architectures tailored for SHA-3, therefore unlocking new possibilities for secure and high-performance data transmission. [ABSTRACT FROM AUTHOR]

This paper presents a new asymmetric image encryption and hiding algorithm based on SHA-3 and compressive sensing. First, to resist the chosen-plaintext attack (CPA) and the known-plaintext attack (KPA), SHA-3 is employed to calculate the hash values of the plain image, and they are transformed into the initial values of the chaotic map. Second, the plain image is divided into blocks which are processed by sparse transform, scrambling, compressive measurement, and merged. Then they are quantized and scrambled again to get an encrypted image. Third, the encrypted image is filled with zeros to the same size as the plain image. Then three numbers from the hundreds digit, tens digit, and single digit of each pixel are extracted respectively. Finally, the carrier image is transformed by integer wavelet transform (IWT) to get four coefficients, and then the above three numbers are embedded into low-frequency coefficients respectively. By inverse IWT, the carrier image containing secrets (CICS) can be obtained. The experimental results show that the algorithm has strong imperceptibility and key sensitivity. Especially, when the embedding coefficient is set to 1.0, the NC value between the carrier image (CI) and the CICS can reach 0.9999, and the PSNR value can reach about 43 dB.

In this paper, a novel cancellable biometrics technique calledMulti-Biometric-Feature-Hashing (MBFH) is proposed. The MBFH strategy is utilized to actualize a single direction (non-invertibility) biometric shape. MBFH is a typical model security conspire that is distinguished in the utilization of this protection insurance framework in numerous sorts of biometric feature strategies (retina, palm print, Hand Dorsum, fingerprint). A more robust and accurate multilingual biological structure in expressing human loneliness requires a different format to record clients with inseparable comparisons from individual biographical sources. This may raise worries about their utilization and security when these spread out designs are subverted as everybody is acknowledged for another biometric attribute. The proposed structure comprises of four sections: input multi-biometric acquisition, feature extraction, Multi-Exposure Fusion (MEF) and secure hashing calculation (SHA-3). Multimodal biometrics systems that are more powerful and precise in human-unmistakable evidence require various configurations to store a comparative customer that can be contrasted with biometric wellsprings of people. Disparate top words, biometrics graphs can't be denied and change to another request for positive Identifications (IDs) while settling. Cancellable biometrics is may be the special procedure used to recognize this issue. [ABSTRACT FROM AUTHOR]

With the rapid growth of data sources, Big data security in Cloud is a big challenge. Different issues have ascended in the area of Big data security such as infrastructure security, data privacy, data management and data integrity. Currently, Big data processing, analytics and storage is secured using cryptography algorithms, which are not appropriate for Big data protection over Cloud. In this paper, we present a solution for addressing the main issues in Big data security over Cloud. We propose a novel system architecture called the Secure Authentication and Data Sharing in Cloud (SADS-Cloud). There are three processes involved in this paper including (i). Big Data Outsourcing, (ii). Big Data Sharing and (iii). Big Data Management. In Big data outsourcing, the data owners are registered to a Trust Center using SHA-3 hashing algorithm. The MapReduce model is used to split the input file into fixed-size of blocks of data and SALSA20 encryption algorithm is applied over each block. In Big data sharing, data users participate in a secure file retrieval. For this purpose, user's credentials (ID, password, secure ID, and current timestamp, email id) are hashed and compared with that stored in a database. In Big data management, there are three important processes implemented to organize data. They are as follows: Compression using Lemperl Ziv Markow Algorithm (LZMA), Clustering using Density-based Clustering of Applications with Noise (DBSCAN), and Indexing using Fractal Index Tree. The proposed scheme for these processes are implemented using Java Programming and performance tested for the following metrics: Information Loss, Compression Ratio, Throughput, Encryption Time and Decryption Time.

In this paper, a novel cancellable biometrics technique called Multi-Biometric-Feature-Hashing (MBFH) is proposed. The MBFH strategy is utilized to actualize a single direction (non-invertibility) biometric shape.MBFH is a typical model security conspire that is distinguished in the utilization of this protection insurance framework in numerous sorts of biometric feature strategies (retina, palm print, Hand Dorsum, fingerprint). A more robust and accurate multilingual biological structure in expressing human loneliness requires a different format to record clients with inseparable comparisons from individual biographical sources. This may raise worries about their utilization and security when these spread out designs are subverted as everybody is acknowledged for another biometric attribute.The proposed structure comprises of four sections: input multi-biometric acquisition, feature extraction, Multi-Exposure Fusion (MEF) and secure hashing calculation (SHA-3). Multimodal biometrics systems that are more powerful and precise in human-unmistakable evidence require various configurations to store a comparative customer that can be contrasted with biometric wellsprings of people. Disparate top words, biometrics graphs can’t be denied and change to another request for positive Identifications (IDs) while settling. Cancellable biometrics is may be the special procedure used to recognize this issue. [ABSTRACT FROM AUTHOR]

Information is transmitted between multiple insecure routing hops in text, image, video, and audio. Thus, this multi-hop digital data transfer makes secure transmission with confidentiality and integrity imperative. This protection of the transmitted data can be achieved via hashing algorithms. Furthermore, data integrity must be ensured, which is feasible using hashing algorithms. The advanced cryptographic Secure Hashing Algorithm 3 (SHA-3) is not sensitive to a cryptanalysis attack and is widely preferred due to its long-term security in various applications. However, due to the ever-increasing size of the data to be transmitted, an effective improvement is required to fulfill real-time computations with multiple types of optimization. The use of FPGAs is the ideal mechanism to improve algorithm performance and other metrics, such as throughput (Gbps), frequency (MHz), efficiency (Mbps/slices), reduction of area (slices), and power consumption. Providing upgraded computer architectures for SHA-3 is an active area of research, with continuous performance improvements. In this article, we have focused on enhancing the hardware performance metrics of throughput and efficiency by reducing the area cost of the SHA-3 for all output size lengths (224, 256, 384, and 512 bits). Our approach introduces a novel architectural design based on pipelining, which is combined with a simplified format for the round constant (RC) generator in the Iota (ι) step only consisting of 7 bits rather than the standard 64 bits. By reducing hardware resource utilization in the area and minimizing the amount of computation required at the Iota (ι) step, our design achieves the highest levels of throughput and efficiency. Through extensive experimentation, we have demonstrated the remarkable performance of our approach. Our results showcase an impressive throughput rate of 22.94 Gbps and an efficiency rate of 19.95 Mbps/slices. Our work contributes to advancing computer architectures tailored for SHA-3, therefore unlocking new possibilities for secure and high-performance data transmission.

This paper presents a new asymmetric image encryption and hiding algorithm based on SHA-3 and compressive sensing. First, to resist the chosen-plaintext attack (CPA) and the known-plaintext attack (KPA), SHA-3 is employed to calculate the hash values of the plain image, and they are transformed into the initial values of the chaotic map. Second, the plain image is divided into blocks which are processed by sparse transform, scrambling, compressive measurement, and merged. Then they are quantized and scrambled again to get an encrypted image. Third, the encrypted image is filled with zeros to the same size as the plain image. Then three numbers from the hundreds digit, tens digit, and single digit of each pixel are extracted respectively. Finally, the carrier image is transformed by integer wavelet transform (IWT) to get four coefficients, and then the above three numbers are embedded into low-frequency coefficients respectively. By inverse IWT, the carrier image containing secrets (CICS) can be obtained. The experimental results show that the algorithm has strong imperceptibility and key sensitivity. Especially, when the embedding coefficient is set to 1.0, the NC value between the carrier image (CI) and the CICS can reach 0.9999, and the PSNR value can reach about 43 dB. [ABSTRACT FROM AUTHOR]

Biometric systems proven to be one of the most reliable and robust method for human identification. Integration of biometrics among the standard of living provokes the necessity to vogue secure authentication systems. The use of palm-prints for user access and authentication has increased in the last decade. To give the essential security and protection benefits, conventional neural networks (CNNs) has been bestowed during this work. The combined CNN and feature transform structure is employed for mapping palm-prints to random base-n codes. Further, secure hash algorithm (SHA-3) is used to generate secure palm-print templates. The proficiency of the proposed approach has been tested on PolyU, CASIA and IIT-Delhi palm-print datasets. The best recognition performance in terms of Equal Error Rate (EER) of 0.62% and Genuine Acceptance Rate (GAR) of 99.05% was achieved on PolyU database. [ABSTRACT FROM AUTHOR]

With the rapid growth of data sources, Big data security in Cloud is a big challenge. Different issues have ascended in the area of Big data security such as infrastructure security, data privacy, data management and data integrity. Currently, Big data processing, analytics and storage is secured using cryptography algorithms, which are not appropriate for Big data protection over Cloud. In this paper, we present a solution for addressing the main issues in Big data security over Cloud. We propose a novel system architecture called the Secure Authentication and Data Sharing in Cloud (SADS-Cloud). There are three processes involved in this paper including (i). Big Data Outsourcing, (ii). Big Data Sharing and (iii). Big Data Management. In Big data outsourcing, the data owners are registered to a Trust Center using SHA-3 hashing algorithm. The MapReduce model is used to split the input file into fixed-size of blocks of data and SALSA20 encryption algorithm is applied over each block. In Big data sharing, data users participate in a secure file retrieval. For this purpose, user's credentials (ID, password, secure ID, and current timestamp, email id) are hashed and compared with that stored in a database. In Big data management, there are three important processes implemented to organize data. They are as follows: Compression using Lemperl Ziv Markow Algorithm (LZMA), Clustering using Density-based Clustering of Applications with Noise (DBSCAN), and Indexing using Fractal Index Tree. The proposed scheme for these processes are implemented using Java Programming and performance tested for the following metrics: Information Loss, Compression Ratio, Throughput, Encryption Time and Decryption Time. [ABSTRACT FROM AUTHOR]

In this article we address the problem of efficient and secure monitoring of computer network traffic. We proposed, implemented, and tested a hardware-accelerated implementation of a network probe, using the DE5-Net FPGA development platform. We showed that even when using a cryptographic SHA-3 hash function, the probe uses less than 17% of the available FPGA resources, offering a throughput of over 20 Gbit/s. We have also researched the problem of choosing an optimal hash function to be used in a network probe for addressing network flows in a flow cache. In our work we compared five 32-bit hash functions, including two cryptographic ones: SHA-1 and SHA-3. We ran a series of experiments with various hash functions, using traffic replayed from the CICIDS 2017 dataset. We showed that SHA-1 and SHA-3 provide flow distributions as uniform as the ones offered by the modified Vermont hash function proposed in 2008 (i.e., with low means and standard deviations of the bucket occupation), yet assuring higher security against potential attacks on a network probe. [ABSTRACT FROM AUTHOR]

Pemantauan kondisi suatu keadaan dengan menggunakan sensor semakin dibutuhkan untuk mengamati perubahan kondisi dari waktu ke waktu. Data-data yang didapatkan sensor kemudian dikirimkan ke sistem pengumpul yang telah disiapkan melalui saluran jaringan telekomunikasi. Pengirimanan data pada perangkat-perangkat jaringan telekomunikasi yang disebar pada lokasi-lokasi tertentu yang kurang aman diberbagai keadaan memungkinkan data tersebut rentan untuk diambil dan dipalsukan. Sistem pengamanan berupa kriptografi dan hashing kemudian digunakan untuk melindungi data agar sampai dengan baik ke penerima. Pada penelitian ini diterapkan sistem keamanan dengan mengimplementasikan algoritma kriptografi asimetrik RSA 2048 bit dan algoritma hashing SHA-3 pada pengiriman paket data yang dikirim. Hal ini dilakukan agar data bisa terjaga keasliannya dan tidak bisa dibaca oleh orang yang tidak berhak jika data tersebut didapatkan. Setelah dilakukan pengujian dengan mengirimkan paket data dari pengirim ke penerima dengan beberapa variasi jarak, didapatkan bahwa ada selisih waktu saat data dikirimkan tanpa menggunakan keamanan dan saat menggunakan keamanan SHA-3 dan RSA 2048 sebesar 70,96603 ms.

Cryptography has become one of the vital disciplines for information technology such as IoT (Internet Of Things), IIoT (Industrial Internet Of Things), I4.0 (Industry 4.0), and automotive applications. Some fundamental characteristics required for these applications are confidentiality, authentication, integrity, and nonrepudiation, which can be achieved using hash functions. A cryptographic hash function that provides a higher level of security is SHA-3. However, in real and modern applications, hardware implementations based on FPGA for hash functions are prone to errors due to noise and radiation since a change in the state of a bit can trigger a completely different hash output than the expected one, due to the avalanche effect or diffusion, meaning that modifying a single bit changes most of the desired bits of the hash; thus, it is vital to detect and correct any error during the algorithm execution. Current hardware solutions mainly seek to detect errors but not correct them (e.g., using parity checking or scrambling). To the best of our knowledge, there are no solutions that detect and correct errors for SHA-3 hardware implementations. This article presents the design and a comparative analysis of four FPGA architectures: two without fault tolerance and two with fault tolerance, which employ Hamming Codes to detect and correct faults for SHA-3 using an Encoder and a Decoder at the step-mapping functions level. Results show that the two hardware architectures with fault tolerance can detect up to a maximum of 120 and 240 errors, respectively, for every run of KECCAK-p, which is considered the worst case. Additionally, the paper provides a comparative analysis of these architectures with other works in the literature in terms of experimental results such as frequency, resources, throughput, and efficiency. [ABSTRACT FROM AUTHOR]

The secure hash function has become the default choice for information security, especially in applications that require data storing or manipulation. Consequently, optimized implementations of these functions in terms of Throughput or Area are in high demand. In this work we propose a new conception of the secure hash algorithm 3 (SHA-3), which aim to increase the performance of this function by using pipelining, four types of pipelining are proposed two, three, four, and six pipelining stages. This approach allows us to design data paths of SHA-3 with higher Throughput and higher clock frequencies. The design reaches a maximum Throughput of 102.98 Gbps on Virtex 5 and 115.124 Gbps on Virtex 6 in the case of the 6 stages, for 512 bits output length. Although the utilization of the resource increase with the increase of the number of the cores used in each one of the cases. The proposed designs are coded in very high-speed integrated circuits program (VHSIC) hardware description language (VHDL) and implemented in Xilinx Virtex-5 and Virtex-6 A field-programmable gate array (FPGA) devices and compared to existing FPGA implementations. [ABSTRACT FROM AUTHOR]