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AlGaAs is a promising integrated nonlinear photonics material with enormous optical nonlinearity and high refractive index. Nevertheless, presently AlGaAs microring resonators exhibiting high-quality factors and tight optical confinement rely predominantly on wafer bonding techniques, which entail an intricate fabrication process. Here, we present suspended AlGaAs waveguides and resonators as a viable platform for high efficiency integrated nonlinear photonics. The suspended microring resonator formed by combined plasma dry etching and chemical wet etching exhibits an intrinsic quality factor Q of 2.1 × 10 6 , corresponding to an optical loss of 0.28 dB/cm, and Kerr comb generation with milliwatt level threshold is recorded. The proposed scheme can be implemented with a relatively simple fabrication process, as it eliminates the need for wafer bonding. Without the hinderance of SiO 2 or Al 2 O 3 claddings, the air-clad suspended AlGaAs platform lends itself directly to applications in the mid-infrared region. Our demonstration opens up a prospect for employing AlGaAs devices in integrated nonlinear photonics. [ABSTRACT FROM AUTHOR]

3D neuromorphic hardware system is first demonstrated in neuromorphic application as on‐chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non‐volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware‐based neural system, considering the possibility of device degradation in both volatile and non‐volatile memory devices demonstrated by the hardware neural system. [ABSTRACT FROM AUTHOR]

In this study, we focus on the development of key processes towards wafer-scale 3-dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP electronics via adhesive bonding. First, we identified the most critical steps and optimized them to achieve high thermal and mechanical compatibility of components for the co-integration process. Next, we developed a strategy for InP-to-InP wafer bonding with high topology tolerance, and introduced hard benzocyclobutene (BCB) anchors to preserve the alignment and BCB thickness uniformity after bonding. The resulting bond layer is homogeneous in terms of physical and mechanical properties. Finally, we developed a novel method to selectively remove the InP substrate from the photonics side via wet etching while protecting the electronics carrier wafer with hermetic multi-layer coatings. The investigation of these key steps is essential for scalable 3D integration of photonics and electronics at ultra short distances (< $15 ~\mu \text{m}$). [ABSTRACT FROM AUTHOR]

This paper introduces a cost-effective, high-performance approach to achieving wafer level vacuum packaging (WLVP) for MEMS-based uncooled infrared sensors. Reliable and hermetic packages for MEMS devices are achieved using a cap wafer that is formed using two silicon wafers, where one wafer has precise grating/moth-eye structures on both sides of a double-sided polished wafer for improved transmission of over 80% in the long-wave infrared (LWIR) wavelength region without the need for an AR coating, while the other wafer is used to form a cavity. The two wafers are bonded using Au-In transient liquid phase (TLP) bonding at low temperature to form the cap wafer, which is then bondelectrical and Electronics d to the sensor wafer using glass frit bonding at high temperature to activate the getter inside the cavity region. The bond quality is assessed using three methods, including He-leak tests, cap deflection, and Pirani vacuum gauges. Hermeticity is confirmed through He-leak tests according to MIL-STD 883, yielding values as low as 0.1 × 10−9 atm·cc/s. The average shear strength is measured as 23.38 MPa. The package pressure varies from 133–533 Pa without the getter usage to as low as 0.13 Pa with the getter usage. [ABSTRACT FROM AUTHOR]

Gallium Phosphide (GaP) has recently received considerable attention as a suitable material for building photonic integrated circuits due to its remarkable optical and piezoelectric properties. Usually, GaP is grown epitaxially on III–V substrates to keep its crystallinity and later transferred to silicon wafers for further processing. Here, an alternative promising route for the fabrication of optomechanical (OM) cavities on GaP epitaxially grown on nominally (001)‐oriented Si is introduced by using a two‐step process consisting of a low‐temperature etching of GaP followed by selective etching of the underneath silicon. The low‐temperature (–30 °C) during the dry‐etching of GaP hinders the lateral etching rate, preserving the pattern with a deviation between the design and the pattern in the GaP layer lower than 5%, avoiding the complex process of transferring and bonding a GaP wafer to a silicon‐on‐insulator wafer. To demonstrate the quality and feasibility of the proposed fabrication route, suspended OM cavities are fabricated and experimentally characterized. The cavities exhibit optical quality factors between 103 and 104 at telecom wavelengths, and localized mechanical resonances ≈3.1 GHz with quality factors ≈63 when measured at room temperature. These results suggest a simple and low‐cost way to build GaP‐based photonic devices directly integrated on industry‐standard Si(001) photonic wafers. [ABSTRACT FROM AUTHOR]

Fast atom beam (FAB) source is used for surface activated bonding. This process is attracting attention as an essential process for next-generation semiconductor manufacturing. Traditional wafer direct bonding processes require annealing or cannot be directly bonded at room temperature. Therefore, there are restrictions on the materials that can be bonded and the combinations of materials that can be bonded. However, surface activated bonding has made it possible to directly bond dissimilar materials at room temperature. This technology is expected to be applied to the manufacturing of various MEMS and three-dimensional stacking of semiconductors. This bonding process involves bombarding the wafer surface with fast argon atom beam in a vacuum chamber. Irradiation removes oxide layer and contaminants, exposing dangling bonds. By pressing the wafers together, the dangling bonds are bonded together, and a strong bond is achieved. The device that generates this fast argon atom beam is FAB source. This device has been of the type that generates a saddle field electric field. However, this FAB source had a narrow beam irradiation area and was unable to support the recent increase in wafer diameter. Therefore, it was necessary to perform irradiation using multiple FAB sources. At production sites, there is a need to develop new FAB sources that can irradiate large areas. In this study, we developed FAB source in which the beam is generated by parallel plate electrodes. We performed a comparison with the saddle field type FAB source and found that the performance was inferior in initial experiments. Next, we improved the design to operate at higher voltages and increased the aperture area. Through these improvements, we have achieved performance superior to the saddle field type FAB source. [ABSTRACT FROM AUTHOR]

The high curing temperatures required for traditional benzocyclobutene (BCB) materials have posed limitations on their applicability in high‐temperature‐sensitive fields. To address this challenge, our work focuses on the synthesis of a novel tetraphenylethylene (TPE)‐functionalized BCB monomer, TPE–BCB, achieved through the introduction of an ether bond onto the BCB's four‐membered ring via Williamson reaction. TPE–BCB demonstrates remarkable low‐temperature curing properties, characterized by a ring‐opening peak temperature of 190°C, representing a reduction of 60°C compared to conventional BCBs. Fully cured TPE–BCB resins exhibit exceptional dielectric and mechanical properties, coupled with minimal water absorption. Additionally, the incorporation of TPE with aggregation‐induced emission characteristics enhances the resins' luminescence and photolithographic capabilities. Notably, our TPE–BCB resins achieve impressive photolithography performance with a resolution ratio of up to 10 μm. In contrast to conventional BCB‐functionalized resins, TPE–BCB offers the dual advantage of low‐temperature curing and luminescence. This development marks a significant step in the advancement of low‐temperature curing BCB materials and serves as a pioneering example in the realm of multilayer wafer bonding materials. [ABSTRACT FROM AUTHOR]

The reduction of the series resistance in multi‐junction solar cells is of high importance for attaining peak efficiencies in concentrator photovoltaics. This study showcases strategies to reduce the sheet resistance of the uppermost subcell of a direct wafer bonded four–junction devices, since it contributes significantly to the series resistance. Therefore, electron mobilities in n–type AlGaInP, lattice matched to GaAs, are investigated across bandgap energies between 1.9 and 2.1 eV and various doping concentrations. The sheet resistances for AlGaInP rear heterojunction cells are determined for the integration in a two terminal four‐junction solar cell. The rear heterojunction cell architecture effectively addresses the sheet resistance optimization because it features a thick n‐type doped absorption layer. The sheet resistance of our current world record quadruple‐junction solar cell with 47.6% efficiency under the 665‐fold concentrated AM1.5d spectrum is 550 Ω sq−1. Herein, it is shown that optimizing the n‐absorption layer in the 1.90 eV GaInP top cell can reduce the sheet resistance to 250 Ω sq−1 without deteriorating the short–circuit current density and current matching. This reduction corresponds to a 5 mΩ cm2 improvement in specific series resistance, which would elevate the efficiency of this device to 48.2%. [ABSTRACT FROM AUTHOR]

High-temperature microfluidic devices (such as gas chromatography microcolumns) have traditionally been fabricated using photolithography, etching, and wafer bonding which allow for precise microscale features but lack the ability to form complex 3D designs. Metal additive manufacturing could enable higher complexity microfluidic designs if reliable methods for fabrication are developed, but forming small negative features is challenging--especially in powder-based processes. In this paper, the formation of sealed metal microchannels was demonstrated using stainless-steel binder jetting with bronze infiltration. To create small negative features, bronze infiltrant must fill the porous part produced by binder jetting without filling the negative features. This was achieved through sacrificial powder infiltration (SPI), wherein sacrificial powder reservoirs (pore size ~60 µm) are used to control infiltrant pressure. With this pressure control, the infiltrant selectively filled the small pores between particles in the printed part (pore size ~3 µm) while leaving printed microchannels (700 µm and 930 µm) empty. To develop the SPI method, a pore filling study was performed in this stainless-steel/bronze system with 370 µm, 650 µm, and 930 µm microchannel segments. This study enabled SPI process design on these length scales by determining variations in pore filling across a sample and preferential filling between different sized pores. [ABSTRACT FROM AUTHOR]

An integrated optical isolator is a crucial part of photonic integrated circuits (PICs). Existing optical isolators, predominantly based on the silicon-on-insulator (SOI) platform, face challenges in integrating with active devices. We propose a broadband, compact TM mode Mach–Zehnder optical isolator based on InP-on-insulator platforms. We designed two distinct magneto-optical waveguide structures, employing different methods for bonding Ce:YIG and InP, namely O2 plasma surface activation direct wafer bonding and DVS-benzocyclobutene (BCB) adhesive bonding. Detailed calculations and optimizations were conducted to enhance their non-reciprocal phase shift (NRPS). At a wavelength of 1550 nm, the direct-bonded waveguide structure achieved a 30 dB bandwidth of 72 nm with a length difference of 0.256 µm. The effects of waveguide arm length, fabrication accuracy, and dimensional errors on the device performance are discussed. Additionally, manufacturing tolerances for three types of lithographic processes were calculated, serving as references for practical manufacturing purposes. [ABSTRACT FROM AUTHOR]

Bodies made from elastically stiff material usually bind very weakly unless the surfaces are flat and extremely smooth. In direct wafer bonding flat surfaces bind by capillary bridges and by the van der Waals interaction, which act between all solid objects. Here we study the dependency of the work of adhesion on the humidity and surface roughness in hydrophilic direct wafer bonding. We show that the long-wavelength roughness (usually denoted waviness) has a negligible influence on the strength of wafer bonding (the work of adhesion) from the menisci that form from capillary condensation of water vapor. AFM surface topography for Si(100) wafer [ABSTRACT FROM AUTHOR]

A new technique is assessed in order to measure, at the wafer scale, direct bonding energies. It is derived from the standard Double Cantilever Beam (DCB) method and uses interferometry in confocal IR laser source microscopy to measure crack openings. Such a bonding energy measurement protocol has better accuracy compared to other techniques. This is due to a better confocal microscopy resolution and the high intensity of the laser source. The elastic energy stored in bent wafers is obtained by measuring the beam curvature. DCB deformation models are discussed from the short-range crack opening theory to long distance beam-bending theories. Comparison is made between models, experimental results, and FEM simulations. Finally, the bonding energy error during standard measurements is estimated. [ABSTRACT FROM AUTHOR]

Room temperature wafer bonding is a desirable approach for the packaging and assembly of diverse electronic devices. The formation of SiO 2 layer at the bonding interface is crucial for a reliable wafer bonding as represented by conventional bonding techniques such as hydrophilic bonding and glass frit bonding. This paper reports a novel concept of room temperature wafer bonding based on the conversion of polysilazane to SiO 2 at the bonding interface. As polysilazane is converted to SiO 2 by hydrolysis, in this work, adsorbed water is introduced to the bonding interface by plasma treatment, thereby facilitating the formation of SiO 2 at the wafer bonding interface. The experimental results indicate that the adsorbed water from the plasma treatment diffuses into the polysilazane layer and facilitates its hydrolysis and conversion. The proposed method demonstrates the successful wafer bonding at room temperature with high bond strength without interfacial voids. This technique will provide a new approach of bonding wafers at room temperature for electronics packaging. [ABSTRACT FROM AUTHOR]

Purpose: Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment. Design/methodology/approach: The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied. Findings: The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency. Originality/value: Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding. [ABSTRACT FROM AUTHOR]

Detecting mechanical fatigue of metallic components is always a challenge in industries. In this work, we proposed to monitor the low-cycle fatigue of a 6061 aluminum alloy based on internal friction (IF) measurement, which is realized by a quantitative electromechanical impedance (Q-EMI) method using a small piezoelectric wafer bonded on the specimen. Large stress amplitude (230 MPa) was employed in the testing; thus, the fatigue life can always be below 105 cycles. It was found that except for the initial testing stage, the IF always increases steadily with the increasing fatigue cycles. Before the fatigue failure, the IF can reach 2.5–3.4 times the initial value, which is thought to be caused by the micro-cracks forming and growing. In comparison, the resonance frequency of the specimen just drops by about 2% compared with the initial value. Finally, a fatigue criterion based on IF measurement is suggested for aluminum alloys and it can also be extended to other metals. [ABSTRACT FROM AUTHOR]

This work investigates substrate leakage in Capacitive Micromachined Ultrasonic Transducers, (CMUTs) having thin backings. CMUTs produced with solid or rigid substrates have a high Q resonance with flat baseline. However, if the operating wavelength of CMUT becomes larger than the thickness of substrate the real part of cell impedance shows elevated baselines with more leakage at DC than at higher frequencies. When a clamped CMUT membrane is excited harmonically the vibrations produced are counterbalanced by the backing medium. Hence some of the energy is coupled to substrate as loss resulting in a lower mechanical Q of resonance. We first derive this energy coupled to the backing medium using FEA analysis considering the velocity field and associated tensile stresses in a thin backing. Substrate impedance is found numerically from isotropic damping of dispersive elastic waves in the backing. This backing impedance is introduced as a shunt mechanical loss across the transduction force in equivalent circuit model. We characterize the measured impedance of CMUT cells with both FEMs and linear circuit models. Simulations results closely agree with the measured impedance levels, frequency and bandwidth of resonance. [ABSTRACT FROM AUTHOR]

The impact of postbond annealing on the structural and thermal characteristics of 130 nm thick exfoliated (201) β-Ga2O3 (via H+ ion implantation) wafer bonded to (0001) 4H-SiC was studied. Thirty nanometer amorphous-Al2O3 was grown on the β-Ga2O3 substrates prior to bonding as an interlayer between β-Ga2O3 and 4H-SiC. The surface activated bonding technique was utilized for bonding, which induces a thin nanometer amorphous interfacial region at the bonded interface (Al2O3|4H-SiC). We demonstrate annealing the bonded structure at 800 °C up to 1 h is beneficial: (1) the removal of residual strain in the exfoliated β-Ga2O3 layer that was due to the exfoliation implant, (2) reduction of lattice mosaicity in the β-Ga2O3 layer, (3) nearly complete recrystallization of the amorphous bonded interfacial region, and (4) partial recrystallization of the initially amorphous-Al2O3 interlayer. The thermal characteristics correspondingly improve with the improvement in structural characteristics. The thermal conductivity of the as-bonded β-Ga2O3 layer was 2.9 W/m K, and the thermal boundary conductance of the bonded interface was 66 MW/m2 K. After annealing at 800 °C for 1 h, triple-axis x-ray diffraction ω:2θ measurements showed a reduction in strain for the β-Ga2O3 layer and the symmetric (201) rocking curve widths. We simultaneously observe a doubling of the β-Ga2O3 thermal conductivity to 6.0 W/m K and a 20% increase in the thermal boundary conductance. However, upon further annealing up to 10 h and fully recrystallizing both the Al2O3 interlayer and bonded interface, the thermal boundary conductance dropped by ∼30%. This preliminary result suggests that crystalline heterointerfaces may not necessarily be the most optimal interfacial structure for thermal transport. [ABSTRACT FROM AUTHOR]

Ambient mass spectrometry imaging (MSI) is a powerful technique that allows for the simultaneous mapping of hundreds of molecules in biological samples under atmospheric conditions, requiring minimal sample preparation. We have developed nanospray desorption electrospray ionization (nano-DESI), a liquid extraction-based ambient ionization technique, which has proven to be sensitive and capable of achieving high spatial resolution. We have previously described an integrated microfluidic probe, which simplifies the nano-DESI setup, but is quite difficult to fabricate. Herein, we introduce a facile and scalable strategy for fabricating microfluidic devices for nano-DESI MSI applications. Our approach involves the use of selective laser-assisted etching (SLE) of fused silica to create a monolithic microfluidic probe (SLE-MFP). Unlike the traditional photolithography-based fabrication, SLE eliminates the need for the wafer bonding process and allows for automated, scalable fabrication of the probe. The chamfered design of the sampling port and ESI emitter significantly reduces the amount of polishing required to fine-tune the probe thereby streamlining and simplifying the fabrication process. We have also examined the performance of a V-shaped probe, in which only the sampling port is fabricated using SLE technology. The V-shaped design of the probe is easy to fabricate and provides an opportunity to independently optimize the size and shape of the electrospray emitter. We have evaluated the performance of SLE-MFP by imaging mouse tissue sections. Our results demonstrate that SLE technology enables the fabrication of robust monolithic microfluidic probes for MSI experiments. This development expands the capabilities of nano-DESI MSI and makes the technique more accessible to the broader scientific community. [ABSTRACT FROM AUTHOR]

The paper presents an analytical model for the design of a composite membrane circular capacitive micromachined ultrasonic transducers (cMUT) cell. The analytical model harnesses composite membrane layer cMUT cell based on the mass-spring-damper system. The effects of damping due to the surrounding medium and acoustic impedance of self-radiation as well as identical neighbouring cells cluster are also modelled for dynamic analysis of unit cMUT cell. The validation of analytically obtained results is performed through FEM simulations using MEMSCAD tool CoventorWare®. The analytically obtained results show good agreement with the FEM simulation results. The designed structure is based on the wafer bonding technology, which is well established at the authors' laboratory. It is a low temperature anodic bonding process without through silicon via/through glass via (TSV/TGV) technique requirement (Aditi et al. in IEEE 24th Electronics Packaging Technology Conference (EPTC), 2022). Composite membrane circular cMUT cell is designed and validated for air-coupled application; moreover, the model developed is also applicable to other fluids as well. [ABSTRACT FROM AUTHOR]

Wafer bonding is a highly effective technique for integrating dissimilar semiconductor materials while suppressing the generation of crystalline defects that commonly occur during heteroepitaxial growth. This method is successfully applied to produce efficient solar cells, making it an important area of research for photovoltaic devices. In this article, a comprehensive review of semiconductor wafer‐bonding technologies is provided, focusing on their applications in solar cells. Beginning with an explanation of the thermodynamics of wafer bonding relative to heteroepitaxy, the functionalities and advantages of semiconductor wafer bonding are discussed. An overview of the history and recent developments in high‐efficiency multijunction solar cells using wafer bonding is also provided. Bonded solar cells made of various semiconductor materials are reviewed and various types of wafer‐bonding methods, including direct bonding and interlayer‐mediated bonding, are described. Additionally, other technologies that utilize wafer bonding, such as flexible cells, thin‐film transfer, and wafer reuse techniques, are covered. [ABSTRACT FROM AUTHOR]

We demonstrate a controllable depletion of the nitrogen buffer gas pressure in a micro-machined cesium (Cs) vapor cell from the dynamic heating of an alkali dispenser pill. When the alkali source is laser activated, the gettering compounds within the alkali pill dispenser reduce the nitrogen (N2) content from the vapor for fine-tuning of the alkali to buffer gas pressure ratio, with a demonstrated pressure step size as low as 1 Torr. Additionally, we decrease the buffer gas pressure below 100 mTorr to evaluate the presence of other potential broadening mechanisms. Real-time control of the gas pressure ratio in the vapor cell will have notable benefits for refining atomic sensor performance and provide a routine to achieve various target pressures across a wafer bonded with a uniform back-filled buffer gas pressure. [ABSTRACT FROM AUTHOR]

Wafer warpage affects the resolution of photolithography, process alignment, and wafer bonding, which leads to the degradation of the device’s yield, performance, and reliability. With the development of devices, the increase of metal layers in the stack direction will worsen the warpage problem. We investigate the Wafer-to-Wafer (W2W) bonding process-induced warpage issue with experiments and a full wafer simulation. A concave wafer warpage of $70~\mu \text{m}$ is observed for a single wafer with a $7.8~\mu \text{m}$ thickness DRAM layer due to the shrinkage of the DRAM layer. In both experiments and simulation, we reveal that the W2W bonding process induces warpage 3 times the single wafer warpage value, as the deformation restriction of the DRAM layers by the thinned Si layer is weak. Furthermore, good agreement is observed between the simulated results and the measured data, which validates the simulation mode. We estimate the wafer warpage of the multi-stack wafer bonding with the validated model. As an example, the warpage of a 4-stack wafer is revealed to be 7 times the single wafer warpage value. This study provides useful information on wafer warpage in the W2W bonding process and reveals the severe warpage issue with increasing the stacked metal layers. [ABSTRACT FROM AUTHOR]

Glass has unique properties that make it attractive for many applications. Combining glass with Si fabrication process would create new possibilities not only in device performance and form factor, but also scale economies. Key challenges in using glass wafers in a Si fab include lack of opacity and electrical conductivity as well as metallic and particle contamination. These challenges can be overcome through a suitable coating on the glass wafer and rigorous particle removal throughput the fabrication and use process. For applications that demand high precision to support direct wafer bonding and lithography, glass wafers can be engineered to deliver the required surface smoothness and flatness. [ABSTRACT FROM AUTHOR]

Wafer bonding of β‐Ga2O3 and N‐polar GaN single crystal substrates is demonstrated by adding ZnO as a "glue" interlayer. The wafers are fully bonded such that Newton rings are not observed. Temperature‐dependent current‐voltage (I–V) measurements are conducted on the as‐bonded Ga2O3/ZnO/N‐polar GaN test structure and after annealing at 600 °C and 1100 °C. The impact of post‐annealing temperature on the electrical and structural characteristics of the bonded samples is investigated. A consistently ohmic‐like characteristic is obtained by annealing the bonded wafers at 1100 °C in N2, which is in part due to crystallization of ZnO and diffusion of Ga into ZnO which makes it n‐type doped. The wafer bonding of β‐Ga2O3 and GaN achieved in this work is promising to combine the material merits of both GaN and Ga2O3 targeting breakthrough high‐frequency and high‐power device performances. [ABSTRACT FROM AUTHOR]

Silicon-based microchannel technology offers unmatched performance in the cooling of silicon pixel detectors in high-energy physics. Although Si–Si direct bonding, used for the fabrication of cooling plates, also meets the stringent requirements of this application (its high-pressure resistance of ~200 bar, in particular), its use is reported to be a challenging and expensive process. In this study, we evaluated two alternative bonding methods, aiming toward a more cost-effective fabrication process: Si-Glass-Si anodic bonding (AB) with a thin-film glass, and Au-Au thermocompression (TC). The bonding strengths of the two methods were evaluated with destructive pressure burst tests (0–690 bar) on test structures, each made of a 1 × 2 cm2 silicon die etched with a tank and an inlet channel and sealed with a plain silicon die using either the AB or TC bonding. The pressure resistance of the structures was measured to be higher for the TC-sealed samples (max. 690 bar) than for the AB samples (max. 530 bar), but less homogeneous. The failure analysis indicated that the AB structure resistance was limited by the adhesion force of the deposited layers. Nevertheless, both the TC and AB methods provided sufficient bond quality to hold the high pressure required for application in high-energy physics pixel detector cooling. [ABSTRACT FROM AUTHOR]

Despite it being known that native oxides impair diffusion processes during eutectic wafer bonding, the possibility of oxide removal combined with avoidance of oxide regrowth on the surfaces is not usually employed in AlGe eutectic wafer bonding. In the present work, the focus is on the impact of different process parameters like temperature, concentration, and oxide regrowth on the AlGe bonding layer, while processing inside ultra-high vacuum. Based on the results, it could be shown that the in situ AlGe eutectic bonding process enables acceptable bonding results already below the eutectic temperature Te = 423 °C, which would be required to liquefy the AlGe bonding layer at the eutectic concentration ce = 28.4 at. % Ge. Even if the AlGe system was not entering the liquid state, solid-state diffusion is sufficient to achieve a high bonding quality. The applied bonding force corresponds to a pressure of ∼0.16 MPa, which is much lower compared to the typical (ex situ) AlGe bonding process. In addition, it could be clarified that extreme variations of concentrations below and above c e were not as critical as expected. A good phase mixture as well as a low number of voids has been observed even if the resulting concentration did not fit c e . The main feature of the bonding system, which is oxide removal while suppressing the oxide re-growth, enhanced the quality of bonding result compared to the regular ex situ eutectic bonding approach. [ABSTRACT FROM AUTHOR]

Germanium-on-insulator (GeOI) films fabricated using the Smart Cut™ wafer bonding and film exfoliation technology were investigated for the mechanical properties and induced phase transformations by using nanoindentation and Raman spectroscopy experiments. The hardness and modulus results of the GeOI films are significantly different from the literature published Silicon-on-Insulator and bulk germanium results. The GeOI films are softer and more flexible as compared to bulk Ge hardness and stiffness properties. The Raman spectroscopy of the spherical indents indicates bands of metastable Ge phases @ 220 cm−1, 195 cm−1, and 184 cm−1 wavenumbers. Our results demonstrate that a spherical indenter impacted a wider area of contact and produced GeOI indented surfaces free of cracks and fracture. The spherical indenter tip kept the Ge top layer intact when compared to the Berkovich indenter tip during penetration. In contrast, the Berkovich indenter tip developed excessive fracture that resulted in displacing the Ge top layer sideways and exposed the Si substrate underneath revealing Raman spectra bands of metastable Si phases @ 350 cm−1, 399 cm−1, and 430 cm−1. [ABSTRACT FROM AUTHOR]

Dark current characteristics of germanium (Ge) vertical p-i-n photodetectors were studied. Ge photodetectors were demonstrated on the germanium-on-insulator (GOI) platforms realized via direct wafer bonding and layer transfer. GOI platforms with two different threading dislocation densities (TDDs) of 3.2 × 106 cm−2 (low TDD) and 5.2 × 108 cm−2 (high TDD) were varied via furnace annealing in oxygen ambient. An ultra-low dark current density of 1.12 mA/cm2 for epi-Ge photodetectors was obtained for a low TDD Ge photodetector. This is reduced by a factor of 53 in comparison with a high TDD Ge photodetector. A dominant leakage contribution component shifts from bulk leakage to surface leakage as TDD decreases to 3.2 × 106 cm−2, suggesting that advanced surface passivation is required to further reduce the leakage current. Through an activation energy study, it is revealed that a primary bulk leakage mechanism shifts from Shockley–Read–Hall (SRH) leakage to diffusion leakage in a temperature range of 323–353 K. The surface leakage performed with plasma enhanced chemical vapor deposition-deposited SiO2 is governed by SRH and trap-assisted tunneling leakage processes. Two orders of magnitude enhancement in the effective carrier lifetime is observed with the reduction in TDD. This work suggests that bulk leakage current density and effective lifetime analysis provide a better understanding of TDD-dependent dark leakage current study. [ABSTRACT FROM AUTHOR]

The availability of thin-film lithium niobate on insulator (LNOI) and advances in processing have led to the emergence of fully integrated LiNbO3 electro-optic devices. Yet to date, LiNbO3 photonic integrated circuits have mostly been fabricated using non-standard etching techniques and partially etched waveguides, that lack the reproducibility achieved in silicon photonics. Widespread application of thin-film LiNbO3 requires a reliable solution with precise lithographic control. Here we demonstrate a heterogeneously integrated LiNbO3 photonic platform employing wafer-scale bonding of thin-film LiNbO3 to silicon nitride (Si3N4) photonic integrated circuits. The platform maintains the low propagation loss (<0.1 dB/cm) and efficient fiber-to-chip coupling (<2.5 dB per facet) of the Si3N4 waveguides and provides a link between passive Si3N4 circuits and electro-optic components with adiabatic mode converters experiencing insertion losses below 0.1 dB. Using this approach we demonstrate several key applications, thus providing a scalable, foundry-ready solution to complex LiNbO3 integrated photonic circuits. Lithium niobate plays an important role in integrated photonics, but its widespread application requires a reliable solution. Here, the authors present a wafer-scale approach to LNOI integration via wafer bonding to silicon nitride PICs. [ABSTRACT FROM AUTHOR]

The development of big data and artificial intelligence technology is increasing the need for electronic devices to become smaller, cheaper, and more energy efficient, while also having enhanced functionalities. However, the miniaturization of silicon chip technology is approaching its Moore's law (i.e., physical) limits. Thus, the application of three-dimensional integrated circuits (3D ICs), in which multiple chips are stacked vertically, provides the most achievable approach for the advancement of post-Moore electronics. In the recent decade, various key techniques have been developed for stacking chips vertically such as through-silicon vias, micro-bumps, low melting point tin–bismuth solders, redistribution layers, and copper-to-copper direct bonding. However, the need for high current densities in these structures results in severe Joule heating, making electromigration (EM) an increasingly challenging problem. This paper reviews studies on EM failures, mechanisms, and potential solutions for the key components of 3D IC packaging. [ABSTRACT FROM AUTHOR]

Small-pitch 3D pixel sensors have been developed to equip the innermost layers of the ATLAS and CMS tracker upgrades at the High Luminosity LHC. They feature 50 × 50 and 25 × 100 μ m 2 geometries and are fabricated on p-type Si–Si Direct Wafer Bonded substrates of 150 μ m active thickness with a single-sided process. Due to the short inter-electrode distance, charge trapping effects are strongly mitigated, making these sensors extremely radiation hard. Results from beam test measurements of 3D pixel modules irradiated at large fluences ( 10 16 n e q / cm 2 ) indeed demonstrated high efficiency at maximum bias voltages of the order of 150 V. However, the downscaled sensor structure also lends itself to high electric fields as the bias voltage is increased, meaning that premature electrical breakdown due to impact ionization is a concern. In this study, TCAD simulations incorporating advanced surface and bulk damage models are used to investigate the leakage current and breakdown behavior of these sensors. Simulations are compared with measured characteristics of 3D diodes irradiated with neutrons at fluences up to 1.5 × 10 16 n e q / cm 2 . The dependence of the breakdown voltage on geometrical parameters (e.g., the n + column radius and the gap between the n + column tip and the highly doped p + + handle wafer) is also discussed for optimization purposes. [ABSTRACT FROM AUTHOR]

The Al/Au alloy was investigated to improve the ohmic characteristic and light efficiency of reflective infrared light-emitting diodes (IR-LEDs). The Al/Au alloy, which was fabricated by combining 10% aluminum and 90% gold, led to considerably improved conductivity on the top layer of p-AlGaAs of the reflective IR-LEDs. In the wafer bond process required for fabricating the reflective IR-LED, the Al/Au alloy, which has filled the hole patterns in Si3N4 film, was used for improving the reflectivity of the Ag reflector and was bonded directly to the top layer of p-AlGaAs on the epitaxial wafer. Based on current-voltage measurements, it was found that the Al/Au alloyed material has a distinct ohmic characteristic pertaining to the p-AlGaAs layer compared with those of the Au/Be alloy material. Therefore, the Al/Au alloy may constitute one of the favored approaches for overcoming the insulative reflective structures of reflective IR-LEDs. For a current density of 200 mA, a lower forward voltage (1.56 V) was observed from the wafer bond IR-LED chip made with the Al/Au alloy; this voltage was remarkably lower in value than that of the conventional chip made with the Au/Be metal (2.29 V). A higher output power (182 mW) was observed from the reflective IR-LEDs made with the Al/Au alloy, thus displaying an increase of 64% compared with those made with the Au/Be alloy (111 mW). [ABSTRACT FROM AUTHOR]

This paper proposes a piezoresistive high-temperature absolute pressure sensor based on (100)/(111) hybrid SOI (silicon-on-insulator) silicon wafers, where the active layer is (100) silicon and the handle layer is (111) silicon. The 1.5 MPa ranged sensor chips are designed with the size as tiny as 0.5 × 0.5 mm, and the chips are fabricated only from the front side of the wafer for simple, high-yield and low-cost batch production. Herein, the (100) active layer is specifically used to form high-performance piezoresistors for high-temperature pressure sensing, while the (111) handle layer is used to single-side construct the pressure-sensing diaphragm and the pressure-reference cavity beneath the diaphragm. Benefitting from front-sided shallow dry etching and self-stop lateral wet etching inside the (111)-silicon substrate, the thickness of the pressure-sensing diaphragm is uniform and controllable, and the pressure-reference cavity is embedded into the handle layer of (111) silicon. Without the conventionally used double-sided etching, wafer bonding and cavity-SOI manufacturing, a very small sensor chip size of 0.5 × 0.5 mm is achieved. The measured performance of the 1.5 MPa ranged pressure sensor exhibits a full-scale output of approximately 59.55 mV/1500 kPa/3.3 VDC in room temperature and a high overall accuracy (combined with hysteresis, non-linearity and repeatability) of 0.17%FS within the temperature range of −55 °C to 350 °C. In addition, the thermal hysteresis is also evaluated as approximately 0.15%FS at 350 °C. The tiny-sized high temperature pressure sensors are promising in various industrial automatic control applications and wind tunnel testing systems. [ABSTRACT FROM AUTHOR]

Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based electronic devices typically requires graphene transfer from its growth substrate to another desired substrate. This key step for device integration must be applicable at the wafer level and meet the stringent requirements of semiconductor fabrication lines. In this work, wet and semidry transfer (i.e. wafer bonding) are evaluated regarding wafer scalability, handling, potential for automation, yield, contamination, and electrical performance. A wafer scale tool is developed to transfer graphene from 150 mm copper foils to 200 mm silicon wafers without adhesive intermediate polymers. The transferred graphene coverage ranges from 97.9 % to 99.2 % for wet transfer and from 17.2 % to 90.8 % for semidry transfer, with average copper contaminations of 4.7 × 1013 (wet) and 8.2 × 1012 atoms/cm2 (semidry). The corresponding electrical sheet resistance extracted from terahertz timedomain spectroscopy varied from 450 to 550 O sq-1 for wet transfer and from 1000 to 1650 O sq-1 for semidry transfer. Although the wet transfer is superior in terms of yield, carbon contamination level, and electrical quality, wafer bonding yields lower copper contamination levels and provides scalability due to existing industrial tools and processes. Our conclusions can be generalized to all 2D materials. [ABSTRACT FROM AUTHOR]

In this study, room-temperature wafer bonding of Al2O3 thin films on Si thermal oxide wafers, which were deposited using atomic layer deposition (ALD), was realized using the surface-activated bonding (SAB) method. Transmission electron microscopy (TEM) observations indicated that these room-temperature-bonded Al2O3 thin films appeared to work well as nanoadhesives that formed strong bond between thermally oxidized Si films. The perfect dicing of the bonded wafer into dimensions of 0.5 mm × 0.5 mm was successful, and the surface energy, which is indicative of the bond strength, was estimated to be approximately 1.5 J/m2. These results indicate that strong bonds can be formed, which may be sufficient for device applications. In addition, the applicability of different Al2O3 microstructures in the SAB method was investigated, and the effectiveness of applying ALD Al2O3 was experimentally verified. This successful SAB of Al2O3 thin films, which is a promising insulator material, opens the possibility of future room-temperature heterogenous integration and wafer-level packaging. [ABSTRACT FROM AUTHOR]

Mark's precise positioning is critical for achieving wafer bonding accuracy. A Mark positioning algorithm is proposed to improve the accuracy and stability of Mark positioning. Shape template matching can effectively reduce the impact of image quality on positioning accuracy, but it can only achieve pixel precision Mark location. On the basis of this method, the algorithm uses the facet model method to extract the sub-pixel edge information for the Mark contour, and combines the sub-pixel traversal strategy to achieve accurate sub-pixel precision Mark location. Simultaneously, the composite template method is proposed for the first time to improve the template information's quality, which effectively improves the robustness of the algorithm to image quality. The simulation results indicate that the algorithm is capable of positioning with an accuracy of approximately 0.04 pixels. The experimental results indicate that the algorithm is capable of positioning with an accuracy of approximately 0.052 pixels and is resistant to image noise and blur, which meets the accuracy and stability requirements for Mark positioning in wafer bonding alignment. • A Mark positioning algorithm based on sub-pixel shape template matching is proposed that enables high-precision mark location during wafer bonding alignment. • The facet model method is used to introduce sub-pixel edge point information for shape template matching, and the sub-pixel positioning is realized combined with the search strategy of sub-pixel step size. • The composite template method is proposed to improve the template quality, which finally improves the reliability of template matching. • Simulation and experiments demonstrate that the algorithm has high positioning accuracy and robustness to image quality. [ABSTRACT FROM AUTHOR]

Anodic bonding is a reliable packaging method for MEMS devices, and the surface properties of the wafer directly affect the bonding efficiency. Therefore, the surface treatment of the wafer to be bonded is necessary. Herein, the effects of three different surface cleaning processes (degreasing, piranha solution and RCA solution) on the wafer surface were investigated by atomic force microscopy, scanning electron microscopy, infrared spectroscopy, and anodic bonding experiments. The analysis showed that during the anodic bonding of the RCA solution-cleaned wafer and Pyrex glass, the bonding interface was more closely attached, and the best surface properties were obtained. The anodic bonding experiments of the wafer and Pyrex glass showed that the bonding current increased with the applied voltage, and the bonding time decreased accordingly. This was most evident in the case of RCA cleaning. The SEM images showed that as the bonding voltage increased, the bonding interface became more uniform without obvious voids. Due to the influence of the strong electric field and temperature field, an irreversible chemical reaction occurred at the bonding interface, which formed a bonding layer that was key to successful bonding. [ABSTRACT FROM AUTHOR]

Single-mode long-wavelength (LW) vertical-cavity surface-emitting lasers (VCSELs) present an inexpensive alternative to DFB-lasers for data communication in next-generation giga data centers, where optical links with large transmission distances are required. Narrow wavelength-division multiplexing systems demand large bit rates and single longitudinal and transverse modes. Spatial division multiplexing transmission through multicore fibers using LW VCSELs is enabling still larger-scale data center networks. This review discusses the requirements for achieving high-speed modulation, as well as the state-of-the-art. The hybrid short-cavity concept allows for the realization of f3dB frequencies of 17 GHz and 22 GHz for 1300 nm and 1550 nm range VCSELs, respectively. Wafer-fusion (WF) concepts allow the realization of long-time reliable LW VCSELs with a record single-mode output power of more than 6 mW, 13 GHz 3 dB cut-off frequency, and data rates of 37 Gbit/s for non-return-to-zero (NRZ) modulation at 1550 nm. [ABSTRACT FROM AUTHOR]

In response to the increasing manufacturing complexity/cost in maintaining DRAM advancements through traditional scaling, three-dimensional integrated circuits (3D ICs) and 2.5-dimensional ICs with Si interposers are known as promising candidates to overcome these challenges due to their advantages of low power, small form factor, high density, and high bandwidth. In this work, we present a true process-heterogeneous stacked embedded DRAM (SeDRAM) using hybrid bonding 3D integration process, achieving high bandwidth of 34 GBps/Gbit and high energy efficiency of 0.88 pJ/bit. Moreover, the critical factors of the SeDRAM design are presented (e.g., the low data movement energy, high-density physical interface, simplified protocol definition, process compatibility, density extensibility, and hybrid bonding connection fast test by DFT (design for test). Our results and design methodology have paved the way to realize applications of hybrid bonding to high bandwidth and energy efficiency DRAM. More importantly, the SeDRAM solution can also support the maximum storage density of 48 Gbit and the bandwidth capability of TBps. It can greatly alleviate the "memory wall" problem and thus improve its competitiveness in near-memory computing/computing-in-memory fields. [ABSTRACT FROM AUTHOR]

Thin-film lithium niobate (TFLN) photonic integrated circuits (PICs) have emerged as a promising integrated photonics platform for the optical communication, microwave photonics, and sensing applications. In recent years, rapid progress has been made on the development of low-loss TFLN waveguides, high-speed modulators, and various passive components. However, the integration of laser sources on the TFLN photonics platform is still one of the main hurdles in the path toward fully integrated TFLN PICs. Here, we present the heterogeneous integration of InP-based semiconductor lasers on a TFLN PIC. The III–V epitaxial layer stack is adhesively bonded to a TFLN waveguide circuit. In the laser device, the light is coupled from the III–V gain section to the TFLN waveguide via a multi-section spot size converter. A waveguide-coupled output power above 1 mW is achieved for the device operating at room temperature. This heterogeneous integration approach can also be used to realize on-chip photodetectors based on the same epitaxial layer stack and the same process flow, thereby enabling large-volume, low-cost manufacturing of fully integrated III–V-on-lithium niobate systems for next-generation high-capacity communication applications. [ABSTRACT FROM AUTHOR]

Aerosol jet printing (AJP) is an emerging additive manufacturing technology that is gaining increasing attention in the electronic field. Several studies have been carried out on the AJP of conductive, semiconductive, and dielectric polymers for electronic applications. However, wafer bonding is an application that is still uncovered by literature. Therefore, in this work, the AJP of benzocyclobutene (BCB) as a polymeric adhesive for wafer bonding is presented for the first time. A thorough characterization of the processing parameters is carried out to identify the most ideal conditions for printing at a relatively high speed. Then, square patterns are printed, proving the versatility of the AJP technology in terms of the reachable thickness of the deposited BCB patterns. Complex patterns with a resolution of ≈60 µm are also printed. The bonding properties of the BCB are characterized from a morphological and mechanical point of view. In particular, the shear strength of the BCB coatings deposited with AJP is ≈39 MPa and it is comparable with the shear strength of BCB coating deposited by spin‐coating. Consequently, AJP represents a valid alternative for the deposition of polymeric adhesive for wafer bonding. [ABSTRACT FROM AUTHOR]

Orientation-patterned gallium phosphide (OP-GaP) has been grown heteroepitaxially on OP gallium arsenide (GaAs) templates using hydride vapor phase epitaxy (HVPE). The effect of OP-GaAs template fabrication methods of epitaxial-inversion and wafer bonding on the heteroepitaxial OP-GaP growth has been investigated. OP-GaP layers with a growth rate of up to 35 µm/h and excellent domain fidelity were obtained. The growth rate and the domain fidelity have been revealed/studied by scanning electron microscope (SEM). In addition, we demonstrate that the crystalline quality of the individual domains, namely, the substrate-oriented domains (ODs) and the inverted domains (IDs), can be investigated by high-resolution x-ray diffraction reciprocal space mapping (HRXRDRSM), which can also indicate the domain fidelity. Attempts to increase the growth rate and improve the domain fidelity by increasing the III and V group precursors resulted in either an increase in the growth rate in the OP-GaP layers grown on epitaxial inversion OP-GaAs template at the expense of the domain crystalline quality and fidelity or an improvement in the crystalline quality of the domains at the expense of the growth rate in the OP-GaP layers grown on wafer-bonded OP-GaAs templates. In the case of OP-GaP grown on OP-GaAs templates prepared by epitaxial inversion, the crystalline quality of the ODs is better than that of the IDs, but it shows that the quality of the inverted layer in the template influences the quality and fidelity of the grown domains. To the authors' knowledge, exploitation of HRXRDRSM studies on OP-GaP to establish the crystalline quality of its individual domains (ODs and IDs) is the first of its kind. OP-ZnSe grown on OP-GaAs templates has also been included in this study to further emphasize the potential of this method. We propose from this study that once the growth rate is optimized from SEM studies, HRXRDRSM analysis alone can be used to assess the structural quality and to infer the domain fidelity of the OP structures. [ABSTRACT FROM AUTHOR]

The electro-mechanical impedance (EMI) method has been demonstrated to be a powerful tool to detect the small local damages in various engineering structures, due to its high-frequency vibration characteristics. However, this technique is difficult to accurately determine the degree and location of structural damages. In this paper, an inverse analysis combining the measured EMI signatures and the Transfer Matrix Method (TMM) is proposed to identify the damages in the steel rods. A milled groove is introduced into each steel specimen to simulate the local damage. By measuring the EMI signatures of the piezoelectric wafers bonded symmetrically on the upper and lower surfaces of the rectangular specimens respectively, the damage can be detected clearly, as well as natural frequencies being extracted in the relatively lower frequency range. The damage sizes and locations are further determined by connecting the frequency equations and any two measured natural frequencies. Tests on three samples show both damage sizes and locations are accurately detected, which indicates that the present method is quite feasible and effective for damage identification in the bar-type structures. [ABSTRACT FROM AUTHOR]

InGaSb-on-insulator (InGaSb-OI) and InAs/InGaAs/InAs-on-insulator (InAs/InGaAs-OI) structures have been realized on Si by a direct wafer bonding (DWB) technology using atomic-layer-deposition Al2O3. While strain introduced in InGaSb channel layers grown on InAs can enhance the hole mobility of the Sb-based channel layers, a difficult issue of fabricating InGaSb-OI wafers is to obtain a smooth InGaSb surface, which is mandatory for wafer bonding. In this study, the surface of a 20-nm-thick In0.185Ga0.815Sb channel grown on an InAs (100) substrate and an InAs (2.5 nm)/In0.185Ga0.815Sb (20 nm)/InAs (2.5 nm) channel with a 20-nm-thick GaSb buffer layer grown on an InAs (100) substrate by metal-organic chemical vapor deposition have a root mean square of the surface roughness as low as 0.16 and 0.22 nm, respectively, over a scan area of 10 × 10 μm2, which are smooth enough to employ the wafer bonding. As a result, the fabrication of the InGaSb-OI wafers by the DWB and the operation of InGaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) by using the DWB wafers are demonstrated. Also, the performance of InGaSb-OI p-MOSFETs is found to be improved by inserting ultrathin InAs layers between InGaSb and insulating buried oxide layers. An InGaSb-OI and an InAs/InGaAs-OI p-MOSFET under the accumulation-mode operation exhibit a peak mobility of ∼161 and ∼273 cm2/V s, respectively. The channel hole mobility of the InGaSb-OI p-MOSFET is higher than that of the GaSb-on-insulator (GaSb-OI) p-MOSFET and can exceed that of Si p-MOSFETs. [ABSTRACT FROM AUTHOR]

Self-calibration capabilities for flexible pressure sensors are greatly needed for fluid dynamic analysis, structure health monitoring and wearable sensing applications to compensate, in situ and in real time, for sensor drifts, nonlinearity effects, and hysteresis. Currently, very few self-calibrating pressure sensors can be found in the literature, let alone in flexible formats. This paper presents a flexible self-calibrating pressure sensor fabricated from a silicon-on-insulator wafer and bonded on a polyimide substrate. The sensor chip is made of four piezoresistors arranged in a Wheatstone bridge configuration on a pressure-sensitive membrane, integrated with a gold thin film-based reference cavity heater, and two thermistors. With a liquid-to-vapor thermopneumatic actuation system, the sensor can create precise in-cavity pressure for self-calibration. Compared with the previous work related to the single-phase air-only counterpart, testing of this two-phase sensor demonstrated that adding the water liquid-to-vapor phase change can improve the effective range of self-calibration from 3 psi to 9.5 psi without increasing the power consumption of the cavity micro-heater. The calibration time can be further improved to a few seconds with a pulsed heating power. [ABSTRACT FROM AUTHOR]

This paper investigates a moiré-based mark for high-precision wafer bonding alignment. During alignment, the mark is combined with digital grating, which has the benefits of high precision and small size. A digital grating is superimposed on the mark to generate moiré fringes. By performing a phase calculation on the moiré fringe images corresponding to the upper and lower wafers, the relative offset of the upper and lower wafers can be accurately calculated. These moiré fringes are exceptionally stable, thereby enhancing the alignment stability. In this study, through practical experiments, we tested the rationality and practicability of the mark. [ABSTRACT FROM AUTHOR]

In this work, void formation was systematically observed for the glass frit bonding technique as a function of the annealing temperature, annealing time, and annealing ambient. High annealing temperature and long annealing time were adopted to reach the maximum heat flux to avoid voids/bubbles. As demonstrated in the experiments, the voids appearing during glass frit bonding are related to the quantity of byproducts from the combustion of organic matter. The experimental results indicate that solely in air, under vacuum, or annealed for short time, the combustion products cannot be fully degassed, and voids occur. It was shown that the alternating three-step conditioning process including glass liquid forming in air, bubble removal under vacuum, and void filling-up in air can lead to void-free and uniform wafer bonding. The glass frit bonding samples with lots of voids/bubbles were compared to the ones without any defects. [ABSTRACT FROM AUTHOR]

Miniaturized ultrasonic transducer arrays with multiple frequencies are key components in endoscopic photoacoustic imaging (PAI) systems to achieve high spatial resolution and large imaging depth for biomedical applications. In this article, we report on the development of ceramic thin-film PZT-based dual- and multi-frequency piezoelectric micromachined ultrasonic transducer (pMUT) arrays and the demonstration of their PAI applications. With chips sized 3.5 mm in length or 10 mm in diameter, square and ring-shaped pMUT arrays incorporating as many as 2520 pMUT elements and multiple frequencies ranging from 1 MHz to 8 MHz were developed for endoscopic PAI applications. Thin ceramic PZT with a thickness of 9 μm was obtained by wafer bonding and chemical mechanical polishing (CMP) techniques and employed as the piezoelectric layer of the pMUT arrays, whose piezoelectric constant d31 was measured to be as high as 140 pm/V. Benefiting from this high piezoelectric constant, the fabricated pMUT arrays exhibited high electromechanical coupling coefficients and large vibration displacements. In addition to electrical, mechanical, and acoustic characterization, PAI experiments with pencil leads embedded into an agar phantom were conducted with the fabricated dual- and multi-frequency pMUT arrays. Photoacoustic signals were successfully detected by pMUT elements with different frequencies and used to reconstruct single and fused photoacoustic images, which clearly demonstrated the advantages of using dual- and multi-frequency pMUT arrays to provide comprehensive photoacoustic images with high spatial resolution and large signal-to-noise ratio simultaneously. [ABSTRACT FROM AUTHOR]

We propose and demonstrate an efficient grating coupler for integrated SiGe photonic devices. A bottom metal layer is adopted to enhance the coupling efficiency on the wafer backside. A low coupling loss of −1.34 dB and −0.79 dB can be theoretically obtained with optimal parameters for uniform and apodized grating couplers, respectively. The fabrication process is CMOS compatible without need of wafer bonding. The influence of fabrication errors on the coupling efficiency is analyzed in terms of substrate thickness, grating dimension and material refractive index. The results indicate a large tolerance for the deviations in practical fabrication. The measured coupling loss of the uniform grating is −2.7 dB at approximately 1465 nm with a 3 dB bandwidth of more than 40 nm. The proposed grating coupler provides a promising approach to realize efficient chip-fiber coupling for the SiGe photonic integration. [ABSTRACT FROM AUTHOR]