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The Rashba spin–orbit coupling effect, primarily arising from structural-inversion asymmetry in periodic crystals, has garnered considerable attention due to its tunability and potential applications in spintronics. Its capability to manipulate electron spin without an external magnetic field opens new avenues for spintronic device design, particularly in semiconductor technology. Within this framework, 2D Rashba materials hold special interest due to their inherent characteristics, which facilitate miniaturization and engineering capabilities. In this Perspective article, we provide an overview of recent advancements in the research of 2D Rashba materials, aiming to offer a comprehensive understanding of the diverse manifestations and multifaceted implications of the Rashba effect in material science. Rather than merely presenting a list of materials, our approach involves synthesizing various viewpoints, assessing current trends, and addressing challenges within the field. Our objective is to bridge the gap between fundamental research and practical applications by correlating each material with the necessary advancements required to translate theoretical concepts into tangible technologies. Furthermore, we highlight promising avenues for future research and development, drawing from insights gleaned from the current state of the field. [ABSTRACT FROM AUTHOR]

Two-dimensional germanium is considered a promising new channel material to replace silicon owing to its lower effective mass and larger electron–hole mobility. To investigate the transport characteristics of single-layer germanane transistors with gate lengths (Lg) below 5 nm, we utilize an ab initio quantum transport methodology. It was found that the n-type germanane transistors having Lg of 3 and 5 nm satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for the on-state current (Ion), effective delay time, and power-delay products of high-performance (HP) devices. Notably, by introducing a negative capacitive (NC) dielectric layer, the p-type germanane transistor having an Lg of 5 nm is almost able to meet the ITRS demands for HP devices. Despite reducing the gate length to 2 nm through the incorporation of the NC dielectric layer, the on-state currents for both n-type and p-type still satisfy approximately 80% of the ITRS standard. Therefore, monolayer germanane presents promising potential as a channel material in a sub-5 nm scale for HP applications. [ABSTRACT FROM AUTHOR]

For over half a century, traditional silicon-based integrated circuits (ICs) have been the basis of computational electronics and are widely used in computers, cell phones, and other fields. With the rapid development of human society, silicon-based semiconductor technology is approaching its physical and engineering limits. Our increasing diversity of non-traditional computing needs, such as ultra-small, ultra-fast, ultra-low-power wearables, and space radiation protection, is driving the search for new electronic materials. Semiconducting single-walled carbon nanotubes (s-SWCNTs) have many excellent electrical properties, such as high carrier mobility and high ballistic transport, making them strong candidates for new semiconductor materials in the post-Moore era. Carbon-based electronic technology has been developed for over 20 years, and the fundamental issues such as the material purification of s-SWCNTs, preparation prospects of s-SWCNT-based field-effect transistors (CNT FETs), and device physics based on CNT FETs have been basically solved. However, the chiral diversity of s-SWCNTs may lead to problems such as fluctuations in the electrical performance of CNT FETs, limiting the application of s-SWCNTs in high-end ICs. Monochiral s-SWCNTs not only have excellent electrical properties but also have a controllable structure and uniformity, which are crucial for the high-end IC of CNTs. However, some problems exist in the purity and yield of monochiral s-SWCNT preparation and the optimization of monochiral CNT FETs. Therefore, the chiral sorting of CNTs is reviewed in this paper, and the progress of polymer reprocessing in chiral separation is highlighted. Then, the research progress of monochiral CNT FETs is introduced, and possible development directions are summarized and analyzed. Finally, the application prospects of chiral-enriched s-SWCNTs include challenges and future opportunities. [ABSTRACT FROM AUTHOR]

Photonic topological insulators have been widely studied due to the robustness of energy transport via supported edge modes immune to structural disorder. In this work, a topological gap waveguide is constructed by introducing line defect into a topological photonic crystal structure and combining it with a gap waveguide structure, the design of which, therefore, combines the advantages of both topological and gap waveguides. Not only does it give high transmission efficiency but it also enables high robustness for energy transmission under structural defects and sharp bends. Our proposed topological waveguide design can be implemented with conventional semiconductor technology and integrated into optical circuits for communication systems. [ABSTRACT FROM AUTHOR]

The advancement of bio‐ionotronics for the brain‐computer interaction necessitates an exploration of the mechanisms of electron‐ion coupled transport in solid state devices. In this study, a bio‐p–n junction composed of n‐type bacteriorhodopsin and p‐type P3HT are proposed. By leveraging electron‐proton synergistic effects, an opto‐ionotronic bio‐diode capable of performing ionotronic switching and rectification functions is fabricated. The switching behavior of the bio‐diode can be controlled both optically and electrically. Under light illumination, the ionotronic bio‐diode exhibits a rectification effect approaching that of an ideal diode, with a reliability of 99% and a rectification ratio of ≈661. Additionally, this bio‐organic composite ionotronic bio‐diode exhibits wide pH responsiveness, good photostability, and high biocompatibility. The proposed opto‐ionotronic bio‐diode can be utilized as a fundamental component in logic circuits, bridging the gap between semiconductor technology and biological systems, and represents a novel paradigm for the advancement of brain‐computer interaction. [ABSTRACT FROM AUTHOR]

Using lasers to achieve controlled crystallographic phase changes in silicon with high spatial precision promises new manufacturing solutions in semiconductor technologies, including silicon photonics. Recent demonstrations of improved amorphization thicknesses position ultrafast lasers as an optimum tool to meet current challenges. Here, the literature on silicon transformations is reviewed and complemented with new experimental data. This includes amorphization and ablation response as a function of pulse duration (τ = 13.9 to 134 fs at λ = 800 nm) and laser wavelength (λ = 258 to 4000 nm with τ = 200 fs pulses). For pulse duration‐dependent studies on Si(111), the amorphization fluence threshold decreases with shorter durations, emphasizing the significance of non‐linear absorption in the range of considered conditions. For wavelength‐dependent studies, the amorphization threshold increases sharply from λ = 258 to 1030 nm, followed by near‐constant behavior up to λ = 3000 nm. Conversely, the ablation threshold fluence increases in these specified ranges. Differences in the obtained amorphization thicknesses on Si(111) and Si(100) are also discussed, identifying an anomalously large fluence range for amorphization at λ = 258 nm. Finally, the question of the lateral resolution, shown as independent of the interaction nonlinearity is addressed. [ABSTRACT FROM AUTHOR]

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field. [ABSTRACT FROM AUTHOR]

This study presents the development of a highly robust, pressureless, and void-free silver sinter-bonding technology for power semiconductor packaging. A bimodal silver paste containing silver nanoparticles and sub-micron particles was used, with polymethyl methacrylate (PMMA) as an additive to provide additional thermal energy during sintering. This enabled rapid sintering and the formation of a dense, void-free bonding joint. The effects of sintering temperature and PMMA content on shear strength and microstructure were systematically investigated. The results showed that the shear strength increased with rising sintering temperatures, achieving a maximum of 41 MPa at 300 °C, with minimal void formation due to enhanced particle necking facilitated by PMMA combustion. However, at 350 °C, the shear strength decreased to 35 MPa due to cracks and voids at the copper substrate–copper oxide interface caused by thermal expansion mismatch. The optimal PMMA content was found to be 5 wt.%, balancing sufficient thermal energy and void reduction. This pressureless sintering technology demonstrates significant potential for high-reliability applications in power semiconductor modules operating under high-temperature and high-stress conditions. [ABSTRACT FROM AUTHOR]

In this study, the effects of Al2O3 and Y2O3 passivation layers on Ge substrates are investigated to enhance the thermal stability of Ge-based devices. Using X-ray photoelectron spectroscopy, we analyze the growth characteristics and chemical composition of Al2O3, Y2O3, and ZrO2 on Ge. The changes in the crystallinity of ZrO2 on different substrates of Ge, Al2O3/Ge, and Y2O3/Ge configurations are observed via X-ray diffraction. Material properties, including capacitance, flat band voltage shift (ΔVFB), oxide charge trap (Not), interface defect density (Dit), and leakage current, are analyzed using the metal–oxide–semiconductor capacitor, with a particular focus on their electrical characteristics. Additionally, we investigate whether the passivation mechanisms of each material are more suitable for enhancing thermal stability. Overall, this study provides insight into the role of passivation layers in improving the interface and thermal stability of Ge-based devices, offering valuable contributions to the advancement of semiconductor technology. [ABSTRACT FROM AUTHOR]

Recent advancements in the fabrication of Resistive Random Access Memory (ReRAM) devices have led to the development of large-scale crossbar structures. In-memory computing architectures relying on ReRAM crossbars aim to mitigate the processor-memory bottleneck that exists with current complementary metal-oxide semiconductor technology. With this motivation, several synthesis and mapping approaches focusing on the realizations of Boolean functions in the ReRAM crossbars have been proposed earlier. Thus far, the verification of the designs realized on ReRAM crossbars is done either through manual inspection or using simulation-based approaches. Since manual inspections and simulation-based approaches are limited to smaller designs, they cannot be applied to the verification of complex designs on large-scale ReRAM crossbars. Motivated by this, we propose, for the first time, an automatic equivalence checking flow that determines the equivalence between the original function specification (e.g., Majority-inverter Graph) and the crossbar micro-operations file formats. We consider two crossbar structures, zero-transistor, one-memristor (0T1R) and one-transistor, one-memristor (1T1R) to implement the micro-operations. While the micro-operations file format exists for 0T1R crossbar structures, no representations for micro-operations to be executed in 1T1R crossbars exist yet. In this work, we introduce the micro-operation file format for 1T1R crossbar structures to efficiently represent the micro-operations as ReRAM crossbar netlists. Afterwards, we introduce two intermediate data structures, ReRAM Sequence Graph for 0T1R crossbars (ReSG-0T1R) and for 1T1R crossbars (ReSG-1T1R), that are derived from the 0T1R and 1T1R crossbar micro-operations file formats, respectively. These ReSGs are then translated into Boolean Satisfiability (SAT) formula, and then the verification is done by checking the generated SAT formulae against the golden functional specification (represented in Verilog) using Z3 Satisfiability solver. Experimental evaluations confirm the effectiveness of the proposed verification methodology on MCNC and ISCAS benchmarks. [ABSTRACT FROM AUTHOR]

Defect-related spin-to-photon interfaces in silicon promise the realization of quantum repeaters by combining advanced semiconductor and photonics technologies. Recently, controlled creation/erasure of simple carbon interstitial defects have been successfully realised in silicon. This defect has a stable structure near room temperature and coherently emits in the wave-length where the signal loss is minimal in optical fibres used in communication technologies. Our in-depth theoretical characterization confirms the assignment of the observed emission to the neutral charge state of this defect, as arising due to the recombination of a bound exciton. We also identified a metastable triplet state that could be applied as a quantum memory. Based on the analysis of the electronic structure of the defect and its similarities to a known optically detected magnetic resonance centre in silicon, we propose that a carbon interstitial can act as a quantum bit and may realize a spin-to-photon interface in complementary metal-oxide semiconductor-compatible platforms. This work presents a theoretical investigation of the single carbon interstitial (Ci) defect in silicon as a potential candidate for spin-photon interfaces. Computed charge transition levels and optical properties show good agreement with the experimental results and allow assigning the experimentally observed telecom zero-phonon emission (1448 nm) to the neutral Ci defect. [ABSTRACT FROM AUTHOR]

This research presents a comprehensive study of a Schottky diode fabricated using a gold wafer and a bilayer molybdenum disulfide ( MoS 2 ) film. Through detailed simulations, we investigated the electric field distribution, potential profile, carrier concentration, and current–voltage characteristics of the device. Our findings confirm the successful formation of a Schottky barrier at the Au/ MoS 2 interface, characterized by a distinct nonlinear I–V relationship. Comparative analysis revealed that the Au/ MoS 2 diode significantly outperforms a traditional W/Si structure in terms of rectification performance. The Au/ MoS 2 diode exhibited a current density of 1.84 × 10 − 9 A/ cm 2 , substantially lower than the 3.62 × 10 − 5 A/ cm 2 in the W/Si diode. Furthermore, the simulated I–V curves of the Au/ MoS 2 diode closely resembled the ideal diode curve, with a Pearson correlation coefficient of approximately 0.9991, indicating an ideality factor near 1. A key factor contributing to the superior rectification performance of the Au/ MoS 2 diode is its higher Schottky barrier height of 0.9 eV compared to the 0.67 eV of W/Si. This increased barrier height is evident in the band diagram analysis, which further elucidates the underlying physics of Schottky barrier formation in the Au/ MoS 2 junction. This research provides insights into the electronic properties of Schottky contacts based on two-dimensional MoS 2 , particularly the relationship between electronic barriers, system dimensions, and current flow. The demonstration of high-ideality-factor Au/ MoS 2 diodes contributes to the design and optimization of future electronic and optoelectronic devices based on 2D materials. These findings have implications for advancements in semiconductor technology, potentially enabling the development of smaller, more efficient, and flexible devices. [ABSTRACT FROM AUTHOR]

In this paper, a five-level inverter-fed Model Predictive Current Control (MPCC) of Five-Phase Permanent Magnet Synchronous Motor (PMSM) Drive is proposed to enhance the performance of the drive by reducing the torque ripples. The MPCC method provides a good steady-state performance and also this method does not require a weighting factor. Among the various torque ripple minimization techniques, the multilevel inverters attracted more attention in electric drives due to rapid development in semiconductor technology. The performance analysis of a five-level (5L) inverter-fed five-phase PMSM drive is compared with two-level (2L) and three-level (3L) inverter drives under various operational conditions. The effectiveness of the proposed method is analyzed using MATLAB/SIMULINK software and also implemented using a real-time simulator. [ABSTRACT FROM AUTHOR]

Wearable sensors designed for continuous, non‐invasive monitoring of physicochemical signals are important for portable healthcare. Oxide field‐effect transistor (FET)‐type biosensors provide high sensitivity and scalability. However, they face challenges in mechanical flexibility, multiplexed sensing of different modules, and the absence of integrated on‐site signal processing and wireless transmission functionalities for wearable sensing. In this work, a fully integrated wearable oxide FET‐based biosensor array is developed to facilitate the multiplexed and simultaneous measurement of ion concentrations (H+, Na+, K+) and temperature. The FET‐sensor array is achieved by utilizing a solution‐processed ultrathin (≈6 nm thick) In2O3 active channel layer, exhibiting high compatibility with standard semiconductor technology, good mechanical flexibility, high uniformity, and low operational voltage of 0.005 V. This work provides an effective method to enable oxide FET‐based biosensors for the fusion of multiplexed physicochemical information and wearable health monitoring applications. [ABSTRACT FROM AUTHOR]

As the demand for high-density, high-performance technologies in semiconductor systems increases, efforts are being made to mitigate and optimize the issues of high current density and heat generation within interconnects to ensure reliability. While interconnects are the most fundamental pathways for transmitting current signals, there has been relatively little research conducted on them compared to individual unit devices from the perspective of overall system performance. However, as integration density increases, the amount of loss in interconnects also rises, necessitating research and development to minimize these losses. In this study, we propose a method to analyze power efficiency by utilizing the differences between simulation results and measured results of interconnect structures. We confirmed that the difference between theoretical resistance values and actual measured values varies with the contact area ratio between metal lines and vias, and we analyzed the power efficiency based on these differences. Using the findings, we proposed and validated a structure that can improve power efficiency. This study presents a method to analyze power efficiency and suggests ways to achieve higher power efficiency within the limited specifications of interconnects. This contributes to enhancing power efficiency and ensuring reliability, thereby preserving the performance of the overall system in highly integrated semiconductor systems. [ABSTRACT FROM AUTHOR]

Novel sensing applications benefit from multifunctional nanomaterials responsive to various external stimuli such as mechanics, electricity, light, humidity, or pollution. While few such materials occur naturally, the careful design of synergized nanomaterials unifies the cross-coupled properties which are weak or absent in single-phase materials. In this study, 2D MoS2 integrated with ultrathin dielectric oxide layers forms hetero-nanostructures with significant impacts on carrier transport. The ternary TiO2/MoS2/ZnO hetero-nanostructures, along with their individual properties, improve the performance of multifunctional sensing devices. The synthesized hetero-nanostructure exhibits a responsivity of up to 16 mA/W to 700 nm light and responds to 5 ppm ammonia gas at room temperature. These enhancements are attributed to interface charge transfer and photogating effects. The ternary TiO2/MoS2/ZnO hetero-nanostructure is compatible with existing semiconductor fabrication technologies, making it feasible to integrate into flexible, lightweight semiconductor devices and circuits. These results may inspire new photodetectors and sensing devices based on two-dimensional (2D) layered materials for IoT applications. [ABSTRACT FROM AUTHOR]

Tin oxide (SnO2) is one of the important semiconductors used in the application of solar cells because of its chemical–mechanical stability and wide band gap. These properties are very important for the performance development and photoanode optimization of a dye‐sensitized solar cell (DSSC). However, the low conduction band value of SnO2 reduces the photovoltaic efficiency, which limits the application of DSSC. Therefore, the doping strategy was used to increase the sensitivity to the visible light spectrum and change the light absorption properties of SnO2. In this paper, pure SnO2, Ag/SnO2, Pt/SnO2, and Pt/Ag/SnO2 nanoparticles were synthesized at the nanoscale by a simple chemical sol–gel method. To characterize the structure, morphological/chemical properties, optical properties, and surface properties of the synthesized SnO2 nanoparticles, X‐Ray Diffraction (XRD), ultraviolet–visible, Brunauer–Emmett–Teller, Scanning Electron Microscopy (SEM)/Energy Dispersive X‐Ray Spectroscopy (EDX), Transmission Electron Microscopy (TEM), and particle size analysis were respectively used. XRD results showed that the crystal sizes varied between 8.8 and 12.2 nm depending on the doping. Doping processes resulted in reductions in particle sizes. Optical studies resulted in decreases in the band gap with the doping process. The conclusions obtained have shown that Ag doping, and Pt–Ag co‐doping can be promising for use as photoanode materials in semiconductor technology and especially in DSSC applications. [ABSTRACT FROM AUTHOR]

High-precision sensors are of fundamental importance in modern society and technology. Although numerous sensors have been developed, obtaining sensors with higher levels of sensitivity and stronger robustness has always been expected. Here, we propose theoretically and demonstrate experimentally an alternative class of sensors with superior performances based on exotic properties of high-order non-Hermitian topological physics. The frequency shift induced by perturbations for these sensors can show an exponential growth with respect to the size of the device, which can grow well beyond the limitations of conventional sensors. The fully integrated circuit chips have been designed and fabricated in a standard 65-nanometer complementary metal-oxide semiconductor process technology. Not only has the sensitivity of systems less than 10-3 femtofarad been experimentally verified, but these systems are also robust against disorders. Our proposed ultrasensitive integrated circuit sensors can have a wide range of applications in various fields and show an exciting prospect for next-generation sensing technologies. [ABSTRACT FROM AUTHOR]

This study introduces a pioneering design for leaky integrate-and-fire (LIF) neurons by integrating memristor devices with CMOS transistors, thereby forming an innovative hybrid CMOS/memristor neuron circuit. Employing Pt/TaOx/Ta as the memristor device, the proposed model was meticulously implemented and rigorously evaluated using the Cadence Virtuoso simulation environment. The simulation outcomes affirm the effective functionality of the design, marking a significant advancement in hybrid circuit engineering. Notably, the proposed neuron circuit exhibits a compact footprint, attributed to the efficient utilization of hybrid CMOS/memristor gates. This characteristic is poised to address the critical challenge of scaling in current neuromorphic systems, offering a viable pathway to substantially augment density and cater to the escalating demands of advanced computational architectures. The findings of this research hold promising implications for enhancing the efficiency and scalability of neuromorphic systems, setting a new benchmark for future developments in this domain. [ABSTRACT FROM AUTHOR]

The data‐driven machine learning technology used for neural decoding emphasizes the requirements of in vivo and in vitro neural signal acquisition with high spatial and temporal resolution. However, micro‐electrode arrays (MEAs) that simultaneously achieve high spatial and temporal resolution neural signal acquisition are not yet available. Meanwhile, the high data bandwidth of large‐scale MEA brings challenges in power consumption, data transmission, storage, and neural signal processing. This research aims to improve the spatial and temporal resolution of MEA, reduce the cost and time of large‐scale MEA customization through cascading, and reduce the bandwidth of large‐scale MEA through spike compression. Firstly, based on in‐pixel spike detection, a row‐based neural spike readout mechanism and related array circuit to improve the neural spike readout performance and temporal resolution of neural signal acquisition is proposed. To further enhance the spatial resolution and reduce the risk of large‐scale MEA fabrication, the cascading capability of the readout circuit is explored. Lastly, spatial correlation‐based neural spike encoding is proposed to reduce the data bandwidth, achieving a 5.2× compression rate. This is a study on implementing large‐scale MEA through cascaded readout circuits and novel study to utilize the spatial correlation between detected neural spikes for further compression. [ABSTRACT FROM AUTHOR]

The structural stability, electronic and mechanical attributes of the tetragonal carbon (tP8) allotrope at high-pressure are examined in the proposed research. The crystal structure of tP8 carbon is different and possesses unusual properties owing to electron localisation. Moreover, tP8 carbon allotrope exhibits remarkable mechanical stability and resilience, making it a strong contender for various applications owing to its plastic deformation and resistance to fracture. Furthermore, the results of the current work show that the band gap of tP8 carbon increases under high pressures, making it a useful material for nanoelectronic device applications. The present report on high-pressure studies of tP8 carbon will pave the way for novel applications in semiconductor technology and high-pressure material applications. [ABSTRACT FROM AUTHOR]

Perovskite oxide semiconductor is unique for its capability to form epitaxial heterostructures with both dielectric and metallic perovskite oxides. The study underscores the potential of perovskite oxides for multi‐layer stacking, a key aspect in advancing semiconductor technology as silicon‐based devices evolve toward 3D stacked structures. Fabrication of the first double‐level double‐gate field‐effect transistors (DL DG‐FETs) is demonstrated, where each layer is epitaxially grown using all‐perovskite oxides. This resulted in improvements in subthreshold swing, current drivability, and field effect mobility. This innovation not only highlights the distinctive potential of perovskite oxides but also provides new avenues for integration with other perovskite oxides on Si for more advanced electronic functions. [ABSTRACT FROM AUTHOR]

This paper presents a new capacitor charger for energy-harnessing applications such as energy transfer from a low-power battery to a load capacitor. The proposed structure uses a switching technique for step-by-step charging of the load capacitor. It comprises a control section, output stage metal-oxide-semiconductor field-effect transistors, and an external inductor. In order to improve the circuit efficiency under different power transfer scenarios, the switching capacitor charger operates at the boundary of continuous conduction mode and discontinuous conduction mode. Two blocks of peak current controller and zero current detector have been employed in a feedback loop to control the inductor current, which resulted in conduction power dissipation reduction. Also, the circuit with switching at low frequencies significantly reduces the switching loss. The performance of the proposed circuit is demonstrated using theoretical elaborations. In addition, the proposed structure is evaluated and simulated in a 0.18μm standard complementary metal-oxide semiconductor technology. Based on the obtained results, the efficiency of the presented circuit at 15.62mW input power is 96%, and the charging time is about 0.54ms, which is suitable for low-power applications. [ABSTRACT FROM AUTHOR]

Layered (2D) perovskites are an emerging attractive 2D system with enhanced stability to ambient conditions as opposed to their highly unstable three dimensional bulk counterpart. Their uniquely tuneable optical and electrical properties are underpinning a surge of interest in 2D‐photovoltaics. So far, the development of nano‐scale integrated opto‐electronic 2D perovskite devices remains nearly unexplored since they have generally been found to be incompatible with standard top‐down semiconductor nano‐fabrication technologies. Here, following the synthesis of solvent‐stable 2D‐fluorinated phenethylammonium lead iodide perovskite (F‐PEA)2PbI4 (F‐PEAI), planar photodetectors entirely fabricated in atmosphere is demonstrated, exhibiting figures of merit rivalling those of commercial silicon photodiodes. A record large room temperature detectivity (>5 × 1017 Jones), a fast time photoresponse (rise time 1.5 ns), an extraordinarily large linear dynamic range (228 dB), as well as a photo‐responsivity of ≈ 1100 AW−1 are demonstrated for devices on a range of substrates including flexible wearable media without the need for any planarization or any atomically thin dielectric, in stark contrast to other 2D semiconductors. Finally, the suitability of nano‐scale 2D F‐PEAI photodetector arrays with sub‐wavelength pixel size of just 100 nm of use for high definition imaging is demonstrated. [ABSTRACT FROM AUTHOR]

Doping is a key method employed in semiconductor technology for tuning the carrier‐density‐dependent electrical properties. In thermoelectric materials, which are typically heavily doped semiconductors, more impact factors are needed to be considered due to the heavy dose doping compared to normal semiconductors beyond carrier concentration optimization, such as band structure modification, carrier scattering mechanism and even thermal transport property. In this review, the doping effect determined by the intrinsic band features and vice versa the influence of dopants on band structure is first illustrated; and then introduce the approaches to overcoming the dilemma in effective doping caused by the temperature‐dependent optimal carrier concentration. Second, the strategies including rational vacancy design, proper selection of dopants and lattice purification toward high efficient doping and weakened carrier scattering strength are reviewed. Third, the recent discovery of the effect of dopant on thermal transport is highlighted covering the dopant‐induced local lattice distortion and exceptional strong electron‐phonon coupling. Finally, a perspective is given for the doping strategies to further boost the performance of thermoelectric materials. [ABSTRACT FROM AUTHOR]

The electrostatic potential within porous materials critically influences applications like gas storage, catalysis, sensors and semiconductor technology. Precise control of this potential in covalent organic frameworks (COFs) is essential for optimizing these applications. We propose a straightforward method to achieve this by employing electric quadrupolar building blocks. Our comprehensive models accurately reproduce the electrostatic potential in 2D-COFs, requiring only a few parameters that depend solely on local electrostatic properties, independent of the COF's lattice structure and topology. This approach has been validated across various systems, including conjugated and non-conjugated building blocks with different symmetries. We explore single-layer, few-layer, and bulk systems, achieving changes in the potential which exceed one electronvolt. Stacking configurations such as eclipsed AA, serrated AA', and inclined stacking all exhibit the tuning effect with minor variations. Finally, we discuss the impact of these potential manipulations on applications like ion and gas uptake. [ABSTRACT FROM AUTHOR]

High-power lasers play an important role in modern science, industry, and medicine. A significant milestone was reached on 5 December 2022, when Inertial Confinement Nuclear Fusion (ICF) achieved scientific breakeven, releasing more energy than the input laser energy. Additionally, Extreme Ultraviolet Lithography (EUVL) has enabled the development of microchips with 3 nm process nodes, marking a leap in semiconductor technology. These examples, together with the recent achievement of 10 PW (1015 W) laser output, herald remarkable advancements in technology and science. Laser systems are broadly classified based on their operating regimes into two main categories: Continuous Wave (CW) operation, where the laser is continuously pumped and emits a steady beam of light, and the pulsed regime, in which the laser produces single or multiple pulses at various repetition rates. This review will primarily focus on pulsed laser systems, exploring their various types and recent technological advancements. [ABSTRACT FROM AUTHOR]

In few industries does the transfer of industrial leadership play a more significant role in the hegemonic competition between superpowers than in the semiconductor industry. As shown in the case of the United States (US)–Japan semiconductor conflict in the 1980s, who takes the lead will be critical in determining the future trajectory of the hegemonic competition between the US and China. This study examines how economic–security linkages and chip-related factors jointly affect the US–China Chip War and the evolving dynamics in Asia at the regional level. The economy–security nexus responds sensitively to the geopolitical structure and degree of economic dependence. Changes in the geopolitical structure create variations in which the economic–security nexus is sometimes either integrated or separated. Chips are currently the world's most critical technology, evolving quickly to create technological regimes and path dependence. Among the diverse technological features of semiconductors, this study focuses on the industrial position of an individual economy's specialization in the chip value chain. Individual states devise statecraft strategies to maximize their economic security gains and minimize risks. In the semiconductor sector, the joint effects of the economic–security nexus and chip-related factors shape each involved economy's statecraft strategy. This study theoretically reveals the concrete mechanisms through which the changing economic–security nexus shapes the economic statecraft of individual economies in the semiconductor value chain. The study also explores how East Asian economies adopt their own strategies along the spectrum of balancing, hedging, and bandwagoning in the context of competition between superpowers. [ABSTRACT FROM AUTHOR]

Extreme ultraviolet lithography (EUVL) is a leading technology in semiconductor manufacturing, enabling the creation of high-resolution patterns essential for advanced microelectronics. This review highlights recent progress in inorganic metal-oxide-based photoresists, with a focus on their applications in EUVL. The unique properties of zinc-based, tin–oxygen, and IVB group inorganic photoresists are examined, showcasing their enhanced chemical reactivity and precise patterning capabilities. Key advancements include the development of zinc oxide and tin oxide nanoparticles, which demonstrate significant improvements in photon absorption and solubility under extreme ultraviolet exposure. Additionally, the review delves into the photochemical reactions of tin–oxygen clusters and the influence of various ligands on film density and cross-linking. The findings suggest that these inorganic photoresists not only improve photolithographic performance but also hold potential for broader applications, such as pyroelectric infrared sensors and 3D printing. Future research directions are outlined, including the optimization of process parameters, the exploration of new ligand and metal combinations, and the evaluation of the environmental benefits of inorganic photoresists over traditional organic ones. These advancements are poised to further enhance the resolution and patterning capabilities required for next-generation semiconductor devices. [ABSTRACT FROM AUTHOR]

The demand for high‐performance X‐ray detectors leads to material innovation for efficient photoelectric conversion and carrier transfer. However, current X‐ray detectors are often susceptible to chemical and irradiation instability, complex fabrication processes, hazardous components, and difficult compatibility. Here, we investigate a two‐dimensional (2D) material with a relatively low atomic number, Ti3C2Tx MXenes, and single crystal silicon for X‐ray detection and single‐pixel imaging (SPI). We fabricate a Ti3C2Tx MXene/Si X‐ray detector demonstrating remarkable optoelectronic performance. This detector exhibits a sensitivity of 1.2 × 107 μC Gyair−1 cm−2, a fast response speed with a rise time of 31 μs, and an incredibly low detection limit of 2.85 nGyair s−1. These superior performances are attributed to the unique charge coupling behavior under X‐ray irradiation via intrinsic polaron formation. The device remains stable even after 50 continuous hours of high‐dose X‐ray irradiation. Our device fabrication process is compatible with silicon‐based semiconductor technology. Our work suggests new directions for eco‐friendly X‐ray detectors and low‐radiation imaging system. [ABSTRACT FROM AUTHOR]

Device scaling for future semiconductor technologies is driving the adoption of innovative methods for miniaturizing semiconductor chips. One promising approach that has garnered significant interest for sub-10 nm device scaling is area selective deposition (ASD). In this study, we demonstrate the feasibility of ASD of silicon dioxide (SiO2) on –OH terminated surfaces (silicon oxide: SiOx) but not on –NH terminated surfaces (silicon nitride: SiNx) for 2D blanket, 2D patterned, and 3D stacks using a novel precursor: Orthrus. To achieve this, we optimized the SiOx and SiNx layers to enhance the –OH and –NH surface bonds, respectively. Using x-ray photo spectroscopy analysis, we showed that SiO2 selectively deposits on SiOx without any nucleation delay compared to SiNx. We have demonstrated the inherent selective deposition of approximately ∼4 nm on 2D patterned structures and ∼3.7 nm on 3D stacks by fine-tuning the atomic layer deposition process. This selective thickness is >250% compared to a previously shown selective SiO2 deposition process in the literature. Finally, we also showed that the step coverage of selective SiO2 growth in 3D stacks is ∼1. This study highlights the potential pathway for performing ASD of commonly used SiO2 in 3D high-aspect-ratio stacks. [ABSTRACT FROM AUTHOR]

Objective: An accurate measurement of x‐ray beams is expected to reduce the uncertainties associated with estimating radiation risk to patients in clinical settings. To perform assessment tasks based on the readings of a solid‐state detector (SSD) using semiconductor technology, the characteristics of the detector should be elucidated. In this study, we evaluated the measurement accuracy of a new SSD under diagnostic x‐ray beam conditions in terms of air kerma, tube voltage, and half‐value layer (HVL). The performance of the SSD was then compared with those of reference instruments. Methods: The tube voltage was varied within the range of 50–120 kV in steps of 10 kV and the thickness and materials of additional filters were concurrently changed (several combinations were tested). In addition, the dose rate and energy dependence of the SSD were also investigated. These effects were analyzed based on statistical significance tests. Furthermore, the expanded uncertainties in the series of measurements were meticulously calculated. Results: The results showed average relative differences of −3.26 ± 1.33%, 0.44 ± 1.01%, and −2.60 ± 3.31% for air kerma, tube voltage, and HVL, respectively. Furthermore, air kerma did not exhibit any dependence on dose rate and energy, in contrast to tube voltage and HVL measurements. Conclusion: The measurement values of the SSD fall within the acceptable range of uncertainty, highlighting its measurement accuracy and reliability. Furthermore, based on the characteristics elucidated by this study, valuable insights are provided concerning the assurance of appropriate measurement values in clinical settings. [ABSTRACT FROM AUTHOR]

Semiconductor industry is experiencing unprecedented growth, still driven by Moore's law, which is continually delivering devices with improved performance at lower costs. The continuation of this development places the industry in a divergent trade-off between economic attractiveness, technological feasibility, and the need for further performance improvement. Since the mainstream semiconductor technologies are silicon-based, new disruptive innovations are needed to gain additional performance margins. The use of nanowires is the preferred approach for preserving electrostatic control in the MOS transistor channel, and the application of mechanical stress is a booster of carrier mobility. It is in this context that this paper presents the design, fabrication, theoretical modeling, and characterization of a measurement platform to characterize the mechanical tensile stress of extremely narrow Si nanowires as small as 14.2 ± 1.12 nm in width. The proposed measurement platform enables a precise control of uniaxial strain, in terms of both amplitude and location, through the implementation of a stoichiometric Si3N4 pulling strand exerting a high tensile force on silicon nanowires. Reported devices are fabricated using a silicon-on-insulator wafer with fully complementary metal–oxide–semiconductor-compatible processing and top-down approach. It is observed that the mechanical strength of nanostructured Si is size-dependent and increases with miniaturization. Characterization revealed a record tensile strength value of 7.53 ± 0.8% (12.73 ± 1.35 GPa) for the narrowest nanowires fabricated using a top-down approach. [ABSTRACT FROM AUTHOR]

Investigating the intrinsic properties of the Schottky interface between graphene and 3D bulk silicon is crucial. However, the semiconductor technology introduces extra doping and defects in graphene, which significantly disturbs the property of the graphene‐silicon interface. Here, the interface parameters of graphene/n‐Si heterojunction are derived by the damage‐free Hg‐probe capacitance–voltage measurement. Due to its low‐density states, the Fermi level of graphene can be pushed upward, which results in a lower Schottky barrier height (ΦB0) of Hg/graphene/n‐Si (HGS) heterostructure than that of Hg/n‐Si (HS) structure. Additionally, the series resistance (Rs) of HGS becomes lower than that of HS, which can be attributed to the narrowed depletion layer width (WD) and the decreased interface state density (Nit). Furthermore, the frequency characteristic is also investigated. Because of the weak interface state charge trapping–detrapping process and the decreased Nit at high frequency, electrons will accumulate in graphene, and the Fermi level will be pushed up. Hence, the ΦB0 and Rs will decrease with increasing frequency. This study contributes to a deep understanding of the graphene/silicon heterojunction interfaces, which is crucial for designing and optimizing the new electronic and optoelectronic devices based on 2D/3D heterostructure. [ABSTRACT FROM AUTHOR]

Piezoelectric and ferroelectric wurtzite are promising to reshape modern microelectronics because they can be easily integrated with mainstream semiconductor technology. Sc doped AlN (Al1‐xScxN) has attracted much attention for its enhanced piezoelectric and emerging ferroelectric properties, yet the commonly used sputtering results in polycrystalline Al1‐xScxN films with high leakage current. Here, the pulsed laser deposition of single crystalline epitaxial Al1‐xScxN thin films on sapphire and 4H‐SiC substrates is reported. Pure wurtzite phase is maintained up to x = 0.3 with ≤0.1 at% oxygen contamination. Polarization is estimated to be 140 µC cm−2 via atomic scale microscopy imaging and found to be switchable via a scanning probe. The piezoelectric coefficient is found to be five times of the undoped one when x = 0.3, making it desirable for high‐frequency radiofrequency (RF) filters and 3D nonvolatile memories. [ABSTRACT FROM AUTHOR]

The latest edition of the IETE Journal of Research, Volume 70, Number 8, August 2024, contains forty-six articles organized by subject, covering advancements in communications, electromagnetics, computers, control engineering, electronic circuits, instrumentation, medical electronics, and power electronics. The articles explore topics such as spectrum hole detection in IoT networks, acoustic analysis of indigenous languages, D2D self-organization in IoT, leaky wave antennas for V2V communications, and energy-efficient clustering algorithms for WSNs. The journal also features research on MIMO antennas, fault diagnosis in induction motors, and smart irrigation systems using IoT and machine learning. [Extracted from the article]

Semiconductor manufacturing and technology testing are developing at different speeds, and yield loss due to inaccuracies in the testing process which has become an important issue. The integrated circuit test model is applied in this study using an iterative yield prediction method (IYP) to estimate the fabrication yield of future wafers based on their process parameters and electrical characteristics. Additionally, test guardband estimation (TGE) method is proposed to adjust the test guardband to maintain the desired product quality after testing. The proposed iterative yield prediction method is demonstrated using a set of parameters from the IEEE International Roadmap for Devices and Systems (IRDS) 2021. Evaluation of the specifications in the IRDS table reveal shows that IYP can demonstrate the appropriate yield curve as predicted. [ABSTRACT FROM AUTHOR]

This study discusses the technology development direction of industry–academia collaboration patents derived from government-subsidized programs and uses technology network analysis to pinpoint the key technologies developed in government-subsidized programs that align with market needs. The main technologies that play a key role in the government-subsidized industry–academia collaboration technology network for recent years are revealed to be measurement and chemistry technologies. The technologies that bridge the gap between multiple fields within the field of medicine are found to be diagnosis, surgery, and identification technologies; these technologies require further attention and resources from the government and academia. Additionally, semiconductor technology is revealed to play an increasingly crucial role in the government-subsidized industry–academia collaboration network. The findings can serve as a reference for the government to allocate research resources and for enterprises to promote emerging technologies. [ABSTRACT FROM AUTHOR]

Artificial neural networks (ANNs), inspired by the structure and function of the human brain, have achieved remarkable success in various fields. However, ANNs implemented using conventional complementary metal oxide semiconductor technology face significant limitations. This has prompted exploration of nonvolatile memory technologies as potential solutions to overcome these limitations by integrating storage and computation within a single device. These emerging technologies can retain resistance values without power, allowing them to serve as analog weights in ANNs, mimicking the behavior of biological synapses. While promising, these nonvolatile devices often exhibit inherent nonlinear relationships between resistance and applied voltage, complicating training processes and potentially impacting learning accuracy. This article proposes a magnetic synapse device based on the spin–orbit torque effect with geometrically controlled linear and nonlinear response characteristics. The device consists of a magnetic multilayer stack patterned into a designed shape, where the width variation along the current flow direction allows for controllable magnetic domain wall propagation. Through finite element method simulations and experimental studies, we demonstrate that by engineering the device geometry, a linear relationship between the applied current and the resulting Hall resistance can be achieved, mimicking the desired linear weight-input behavior in artificial neural networks. Additionally, this study explores the influence of current pulse width on the response curves, revealing a deviation from linearity at longer pulse durations. The geometric tunability of the magnetic synapse device offers a promising approach for realizing reliable and energy-efficient neuromorphic computing architectures. [ABSTRACT FROM AUTHOR]

Diamond wire sawing is one of the key technologies in semiconductor chip and photovoltaic module manufacturing process. The existence of subsurface damage (SSD) after diamond wire sawing has a great impact on the fracture strength of monocrystalline silicon wafers, which leads to an increase in the waste rate of silicon wafers in subsequent processing. Therefore, it is necessary to evaluate the SSD depth in monocrystalline silicon wafers induced by ultrasonic vibration assisted wire sawing (UAWS). In this paper, the equal probability method is used to establish the wire saw surface morphology model. Then, according to the vibration dynamic equation of the wire saw under transverse ultrasonic, the trajectory equation of any abrasive particle is derived. On this basis, based on the material removal model and indentation fracture mechanics, an analytical prediction model of SSD depth of monocrystalline silicon wafers processed by UAWS was established. Finally, validity of the prediction model is verified by comparing with experimental results. The results show that the average error between the experimental value of the SSD depth and the theoretical value of the prediction model is 9.26%. In the UAWS process, the SSD depth of the wafer decreases with the increase of the wire saw speed and increases with the increase of the wire saw feed speed. Compared with the wire saw speed and wire saw feed rate, the workpiece rotation speed has less effect on SSD depth. The research results can be used to guide the optimization of process parameters. [ABSTRACT FROM AUTHOR]

This article proposed a technique for a low‐power and fast start‐up voltage‐controlled oscillator (VCO) for a high data rate 5 G New Radio (5G‐NR) application. The 5G‐NR high data rate signals require a fast start‐up VCO to accommodate the short pulse width. In this proposed work, a cross‐coupled pair (XCP) is integrated with a center‐tapped orthogonal symmetry inductor placed at the gates of the XCP, forming an inductive booster VCO (IBVCO). The inductive impedance at the gate of the XCP preserve the symmetry signal profile of the output voltage swing while alleviating the intrinsic parasitic capacitance effect and flicker noise effect of the transistor under the absence of the tail current source. The concept proves with the improvement on the phase noise performance and generating a fast start‐up without affecting the VCO bandwidth. The VCO also provides the enhancement of the output voltage swing under low power consumption. The IBVCO has been fabricated in 180 nm complementary metal oxide semiconductor technology and consumes a minimum area of only 0.7 mm2. The IBVCO achieved a 13% tuning range from 3.3 to 3.75 GHz bandwidth with a supply voltage, VDD of 0.7 V. The total power consumption is 1 mW with a corresponding phase noise of −122.60 dBc/Hz and a Figure of Merit (FoM) of 193.48 dBc/Hz at 3.52 GHz carrier center frequency at 1 MHz offset. The start‐up time of the VCO achieved is 5 ns. [ABSTRACT FROM AUTHOR]

Plasma etching is an essential semiconductor manufacturing technology required to enable the current microelectronics industry. Along with lithographic patterning, thin-film formation methods, and others, plasma etching has dynamically evolved to meet the exponentially growing demands of the microelectronics industry that enables modern society. At this time, plasma etching faces a period of unprecedented changes owing to numerous factors, including aggressive transition to three-dimensional (3D) device architectures, process precision approaching atomic-scale critical dimensions, introduction of new materials, fundamental silicon device limits, and parallel evolution of post-CMOS approaches. The vast growth of the microelectronics industry has emphasized its role in addressing major societal challenges, including questions on the sustainability of the associated energy use, semiconductor manufacturing related emissions of greenhouse gases, and others. The goal of this article is to help both define the challenges for plasma etching and point out effective plasma etching technology options that may play essential roles in defining microelectronics manufacturing in the future. The challenges are accompanied by significant new opportunities, including integrating experiments with various computational approaches such as machine learning/artificial intelligence and progress in computational approaches, including the realization of digital twins of physical etch chambers through hybrid/coupled models. These prospects can enable innovative solutions to problems that were not available during the past 50 years of plasma etch development in the microelectronics industry. To elaborate on these perspectives, the present article brings together the views of various experts on the different topics that will shape plasma etching for microelectronics manufacturing of the future. [ABSTRACT FROM AUTHOR]

With the increasing development of semiconductors materials and technology, higher demands are emphasized on the packaging methods and materials for the high-temperature electronics. In this investigation, a novel packaging method by eutectic SnIn solder foils using transient liquid phase (TLP) bonding without pressure was introduced, and the microstructures as well as performance evolution of joint bonded at different bonding parameters were analyzed. During the bonding process, the solder alloy as well as weak Cu2In were gradually consumed, and full Cu6(In, Sn)5 bondline could be obtained without any obvious defects at only 200 °C. Higher temperature and longer time could give a further enhancement on the microstructure and the mechanical performance, where dense robust Cu3(In, Sn) bondline formed. Owing to the microstructure optimization, the average shear strength of bonded joint increased by 301.87%. With the great performance and eco-efficiency, this novel TLP-bonding method using SnIn solder foil is capable to meet the increasing requirement of high-temperature packaging. [ABSTRACT FROM AUTHOR]

As technology progresses, the operational frequencies of electronic devices have migrated into the GHz range. As an important electronic device, the compatibility of the preparation process of inductors with integrated circuits also needs to be improved. Currently, most commercial inductors are constructed from ferrite materials, making them challenging to integrate with integrated circuits. Herein, FeCoB films with a self‐biased ferromagnetic frequency up to 21 GHz are deposited on Si substrates using the compositional gradient sputtering method as a magnetic underlayer. A reasonable inductance structure is designed using HFSS simulation software. A series of planar spiral inductors with various turns are fabricated by photolithographic micromachining on the FeCoB films with a polyimide insertion between them. The preparation process is completely based on semiconductor technology and has good compatibility with integrated circuits. The results show that the inductance L and quality factor Q are greatly improved by the introduction of high‐frequency FeCoB film. The inductance is improved by 71% and the quality factor is improved by 166%. This clearly demonstrates that FeCoB thin films are highly suitable for use as inductor cores and can be seamlessly integrated with integrated circuits, offering excellent prospects for use in high‐frequency integrated circuits. [ABSTRACT FROM AUTHOR]

Power electronics plays a key role in the management and conversion of electrical energy in a variety of applications, including the use of renewable energy sources such as solar, wind and hydrogen energy, as well as in electric vehicles, industrial technologies, homes and smart grids. These technologies are essential for the successful implementation of the green transition, as they help reduce carbon emissions and promote the production and consumption of cleaner and more sustainable energy. The present work presents a new generation of power electronic devices and systems, which includes the following main aspects: advances in semiconductor technologies, such as the use of silicon carbide (SiC) and gallium nitride (GaN); nanomaterials for the realization of magnetic components; using a modular principle to construct power electronic devices; applying artificial intelligence techniques to device lifecycle design; and the environmental aspects of design. The new materials allow the devices to operate at higher voltages, temperatures and frequencies, making them ideal for high-power applications and high-frequency operation. In addition, the development of integrated and modular power electronic systems that combine energy management, diagnostics and communication capabilities contributes to the more intelligent and efficient management of energy resources. This includes integration with the Internet of Things (IoT) and artificial intelligence (AI) for automated task solving and work optimization. [ABSTRACT FROM AUTHOR]

MicroIC enables display attributes unattainable from polycrystalline thin‐film transistors, and the complimentary metal‐oxide semiconductor (CMOS) microICs support a wide range of applications beyond driving pixels. Integrating sensors within displays can add value to products, reduce costs and improve performance versus conventional solutions. As evidenced by touch and display integration in mobile displays via TDDI ICs, in‐cell sensing can reduce cost and improve performance to levels that are not available with all display types. Capacitive touch, optical touch, 3D scanning, and proximity sensing can also benefit from the inherent coordination between sensors and display. We present multiple sensing architectures and demonstrations of integration within microLED displays and describe CMOS microIC circuits for touch sensing applications. With diverse heterogenous semiconductor technology tightly woven into displays, the potential for intuitive gesture controls, adaptive interfaces, and enhanced sensory feedback paves the way for more natural and effortless interactions between humans and machines. [ABSTRACT FROM AUTHOR]