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The BABAR detector at PEP-II will operate in a high-luminosity e/sup +/e/sup -/ collider environment near the /spl Upsi/(4S) resonance with the primary goal of studying CP violation in the B meson system. In this environment, typical physics events of interest involve multiple charged particles. These events are identified by counting these tracks in a fast first level (Level 1) trigger system, by reconstructing the tracks in "real time". For this purpose, a Binary Link Tracker Module (BLTM) was designed and fabricated for the BABAR Level 1 Drift Chamber trigger system. The BLTM is responsible for linking track segments, constructed by the Track Segment Finder Modules (TSFM), into complete tracks. A single BLTM module processes a 360 MBytes/s stream of segment hit data, corresponding to information from the entire Drift Chamber, and implements a fast and robust algorithm that tolerates high hit occupancies as well as local inefficiencies of the Drift Chamber. The algorithms and the necessary control logic of the BLTM were implemented in Field Programmable Gate Arrays (FPGAs), using the VHDL hardware description language. The finished 9U/spl times/400 mm Euro-format board contains roughly 75,000 gates of programmable logic or about 10,000 lines of VHDL code synthesized into five FPGAs.

A 250,000 transistor full custom integrated circuit for the readout of drift chamber signals has been developed, produced and characterized. The "Elefant" (ELEctronics For Amplitude 'N Timing) Digitizer IC is designed to measure both the charge and the single electron time of arrival of sense wire signals from the BaBar drift chamber. By combining a FADC (flash analog-to-digital converter) and a TDC (time-to-digital converter) for each channel, the digitizer IC can be optimized and simplified, to achieve the physics goals required of the drift chamber while reducing the per channel costs of the electronics. The Elefant IC also implements portions of the BaBar trigger protocols to simplify the connection of the chip to the rest of the BaBar detector. Each IC contains eight complete independent channels. The circuit has been implemented in a 0.8 /spl mu/m triple metal CMOS process and fabricated in production quantity to fully instrument the BaBar drift chamber and are now in operation. Performance results of the IC will be presented.

The first portion of the BABAR experiment Level 1 Drift Chamber Trigger pipeline is the Track Segment Finder (TSF). Using a novel method incorporating both occupancy and drift-time information, the TSF system continually searches for segments in the supercells of the full 7104-wire Drift Chamber hit image at 3.7 MHz. The TSF was constructed to operate in a potentially high beam-background environment while achieving high segment-finding efficiency, deadtime-free operation, a spatial resolution of

This paper discusses the behaviour of a prototype rad-hard version of the chip developed for the readout of the BaBar silicon vertex tracker. A previous version of the chip, implemented in the 0.8 μm HP rad-soft version has been thoroughly tested in the recent times. It featured outstanding noise characteristics and showed that the specifications assumed as target for the tracker readout were met to a very good extent. The next step was the realization of a chip prototype in the rad-hard process that will be employed in the actual chip production. Such a prototype is structurally and functionally identical to its rad-soft predecessor. However, the process parameters being different, and not fully mastered at the time of design, some deviations in the behaviour were to be expected. The reasons for such deviations have been identified and some of them were removed by acting on the points that were left accessible on the chip. Other required small circuit modifications that will not affect the production schedule. The tests done so far on the rad-hard chip have shown that the noise behaviour is very close to that of the rad-soft version, that is fully adequate for the vertex detector readout.

A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using an TDC comprised of a delay locked loop, latch and encoder. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. Eight complete channels of timing and amplitude information are multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are subsequently transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in an 0.8 /spl mu/m triple metal CMOS process. The measured results indicate that the differential non-linearities of the TDC and the FADC are 200 ps and 10 mV, respectively. The integral non-linearities of the TDC and the FADC are 230 ps and 9 mV, respectively.

Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over marry thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2 /spl mu/m and 0.8 /spl mu/m technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better than 135 ps resolution for the TDC circuit.

The transverse momentum discriminator module (PTDM) is one of the three main modules used in the level 1 charged particle trigger system of the BABAR detector at PEP-II. It provides trigger decisions for charged particles with a transverse momentum, P/sub t/, greater than a configurable threshold. The transverse momentum discrimination algorithm works by evaluating the curvature of the charged tracks in the 1.5 T axial magnetic field. The capabilities of the PTDM are key to a stable and efficient operation of the BABAR experiment even under severe background conditions.

The environment of the high-luminosity PEP-II machine poses unique design challenges for the trigger system of the BABAR detector. These led to the adoption of a real-time parallel pipelined architecture for the trigger electronics which departs significantly from previous implementations at conventional e/sup +/e/sup -/ experiments. One challenge for the trigger designer lies in detecting low multiplicity physics events with high efficiency while keeping the background rate within the data acquisition limits. To achieve this difficult task, creative and innovative high-speed trigger algorithms were designed, simulated and implemented in Field Programmable Gate Arrays on printed circuit boards, using advanced CAD/CAE tools. The simulation results indicate that these algorithms will be able to perform all required tasks quickly and efficiently. This paper describes the design of the Level 1 Drift Chamber Trigger System of the BABAR detector, including the trigger algorithms, design and test methodology of the implementation, as well as test and simulation results.

Within its first year of operation, the BaBar Silicon Vertex Tracker (SVT) has accomplished its primary design goal, measuring the z vertex coordinate with sufficient accuracy as to allow the measurement of the time-dependent CP asymmetry in the neutral B-meson system. The SVT consists of five layers of double-sided, AC-coupled silicon-strip detectors of 300 μm thickness with a readout strip pitch of 50–210 μm and a stereo angle of 90° between the strips on the two sides. Detector alignment and performance with respect to spatial resolution and efficiency in the reconstruction of single hits are discussed. In the day-to-day operation of the SVT, radiation damage and protection issues were of primary concern. The SVT is equipped with a dedicated system (SVTRAD) for radiation monitoring and protection, using reverse-biased photodiodes. The evolution of the SVTRAD thresholds on the tolerated radiation level is described. Results on the first-year radiation exposure as measured with the SVTRAD system and on the so far accumulated damage are presented. The implications of test-irradiation results and possible future PEP-II luminosity upgrades on the radiation limited lifetime of the SVT are discussed.

The Silicon Vertex Tracker (SVT) of the BaBar experiment at the PEP-II asymmetric B factory consists of five layers of double-sided, AC-coupled silicon strip detectors. The detectors are readout with a custom IC, capable of simultaneous acquisition, digitization and transmission of data. The SVT geometry is shown and the construction phases of its modules are described in detail, with emphasis on the bending procedures needed for the arch-modules of the outer layers. (C) 2000 Elsevier Science B.V. All rights reserved.

The central drift chamber for the BaBar detector at the SLAC B-factory is based on a hexagonal cell design with 7104 cells arranged in 40 layers and drift gas Helium:isobutane (80%:20%). Performance optimization and integration requirements led to an electronics design that mounts the amplifier-discriminator and digitizing circuitry directly on the endplate. High channel density is achieved using a 4-channel custom amplifier-discriminator IC and an 8-channel custom CMOS TDC/FADC IC on a single circuit board. Data read from the front ends are multiplexed on 4 fiber optic links, and prompt trigger data are sent out continuously on 24 links. Analysis of cosmic ray data demonstrates that the electronics design meets the performance goals for the BaBar drift chamber. The final electronics were installed on the drift chamber in July, 1998. Installation of BaBar on beamline is scheduled for March, 1999. © 1999 IEEE.

The BaBar Drift Chamber is now under construction. We review its design, the progress in the construction of the components, the plan for assembly and stringing and we present test results obtained with a prototype exposed at SLAC to cosmic rays. We also report on projected dE/dx performance from beam tests done with a chamber with a different cell design.

The readout chip designed to process the microstrip signals in the BaBar silicon vertex tracker (SVT), after being realized twice in a radsoft technology has been transferred into the final radhard process. So far the circuit has gone through four different radhard submissions, one aiming at providing a preliminary insight into the characteristics of the radhard chip, the other ones constituting pre-production and production runs. Chips from these submissions have undergone a thorough set of tests addressing functional aspects, noise parameters and effects of radiation on signal and noise behavior. The present paper discusses the results of these tests and describes the final version of the circuit which has been proven to successfully meet the experiment requirements.