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Your search keyword '"S. Pati Tripathi"' showing total 3 results
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3 results on '"S. Pati Tripathi"'

1. Characterization and Modeling of Quantum Dot Behavior in FDSOI Devices

Author

S. Pati Tripathi, S. Bonen, A. Bharadwaj, T. Jager, C. Nastase, S. Iordanescu, G. Boldeiu, M. Pasteanu, A. Nicoloiu, I. Zdru, A. Muller, and S. P. Voinigescu

Subjects
Compact modeling, Coulomb Blockade, cryogenics, semiconductor quantum dot, silicon germanium, silicon-on-insulator, Electrical engineering. Electronics. Nuclear engineering, TK1-9971
Abstract

A compact analytical model is proposed along with a parameter extraction methodology to accurately capture the steady-state (DC) sequential tunneling current observed in the subthreshold region of the transfer $I_{DS}-V_{GS}$ characteristics of MOSFETs at cryogenic temperatures. The model is shown to match measurements of $p$ -MOSFETs and $n$ -MOSFETs manufactured in a commercial 22nm FDSOI foundry technology, with reasonable accuracy across bias conditions and temperature (2 K - 50 K). Furthermore, the extracted model parameters are used to analyze the impact of the gate and drain voltages and of layout geometry on the device characteristics.

Published
2022
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3. Compact Modelling of 22nm FDSOI CMOS Semiconductor Quantum Dot Cryogenic I-V Characteristics

Author

C. Nastase, M. Pasteanu, S. Iordanescu, Sorin P. Voinigescu, S. Bonen, A. Muller, S. Pati Tripathi, and G. Boldeiu

Subjects
Materials science, business.industry, Semiconductor device modeling, Silicon on insulator, Coulomb blockade, Hardware_PERFORMANCEANDRELIABILITY, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, 7. Clean energy, Computer Science::Other, Computer Science::Hardware Architecture, Quantization (physics), CMOS, Hardware_GENERAL, Quantum dot, Qubit, MOSFET, Hardware_INTEGRATEDCIRCUITS, Optoelectronics, business
Abstract

A compact analytical model is reported capturing the effects of Coulomb Blockade and charge quantization on the drain current characteristics of a MOSFET-based semiconductor quantum dot at cryogenic temperatures. It is implemented as a Verilog-A add-on to the foundry-provided MOSFET model to facilitate potential integration in any design kit and allow for simulation of quantum processors that integrate qubits and control electronics on the same die. The model was verified in the 6-50 K temperature range on the measured I-V characteristics of a nanoscale p-MOSFET fabricated in production 22nm FDSOI CMOS technology.

Published
2021
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