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In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1–4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1–4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ∼8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.

We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V. Excellent electrostatics is obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV·μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided.

300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.

In this paper, we present results and discuss issues related to implementation of large scale circuits in extremely thin (ET) SOI CMOS for low power applications. We have demonstrated that we can fabricate low power (LP) CMOS with centered Vts and good Vt uniformity across wafer and wafer to wafer. Using this CMOS, we have fabricated low leakage and high performance ring oscillators (with delay ∼20% faster than the standard 28 nm LP bulk). We have also obtained perfect 2.25M SRAM arrays, functioning down to Vdd of 0.5V, and we have shown that a 10-level BEOL process has minimal impact on device stability.

Two implantation based schemes were explored for ETSOI NFET devices targeted for the 20nm node. Amorphization of the thin SOI is a key issue for the implant pre RSD scheme. This can be alleviated by implanting through liner. Variability is the key issue for the implant post RSD scheme which can be alleviated by good process controls and by the use of a two step epitaxy scheme.

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

We present UTBB devices with a gate length (L G ) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V bb ) enables V t modulation of more than 125mV with a V bb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V t and power management applications. We explore the impact of GP, BOX thickness and V bb on local V t variability for the first time. Excellent A Vt of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I g ) and lower external resistance (R ext ), thanks to a thicker inversion gate dielectric (T inv ) and body (T si ) thickness.

Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2].

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at I off = 300 pA/µm, V DD = 0.9V, and L G = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low V T variability is achieved with A Vt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (R para ) degraded by 3-D structure with thin Si-body. The issue of V t -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently, the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful lithography-design optimization.

Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell, at Vd = 0.6 V, a static noise margin (SNM) of 95 mV was obtained and stable read/write operations were verified from N-curve measurements. sigmaVt of transistors in 0.187 m2 cells was measured with and without channel doping and the result was summarized in the Pelgrom plot. With the 22 nm node design rule, FinFET SRAM cell layouts were compared against planar-FET SRAM cell layouts. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, which would have higher sigmaVt mainly caused by heavy doping into the channel region.

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

MRAM technology offers an attractive combination of performance, density, low power, non-volatility, and write endurance. While first stand-alone MRAM products appear poised for introduction, major technology advances are also being reported. In this review, we discuss our work on a 16Mbit demonstrator chip with a 1.42 /spl mu/m/sup 2/ cell in 180 nm technology in the context of recent world wide advances in MRAM technology. These include a cell architecture that resolves the magnetic half select write disturb issue and an advanced tunnel barrier material, MgO, that promises much larger signals for MRAM read operations.

Current-induced spin-torque switching was demonstrated on sub-100 nm magnetic tunnel junction devices fabricated on 200 mm substrates utilizing 180 nm complimentary metal–oxide–semiconductor back-end-of-the-line (BEOL) technology. Low resistance-area (RA) product and high tunneling magnetoresistance (TMR) were achieved by using substrates containing a CoFeB free layer and a thin MgO barrier. To obtain the desired sub-100 nm features, photoresist trimming was applied on patterns created by a 248 nm lithography tool. Furthermore, the magnetic stack was defined using an ion beam etch that stopped on the thin MgO barrier. Field-sweep measurements on elliptical devices that are 80 nm wide and 160 nm long indicated RA∼4 Ω μm2 and TMR∼90%. Upon injecting current into the devices while applying an external offset field of 28 Oe, current-induced switching occurred from parallel (P) to antiparallel (AP) state at +1.3 mA, and from AP to P state at −1.25 mA. BEOL process integration on 200 mm substrates enabled stati...

Toggle magnetic random access memory (MRAM) has been proposed to solve the problems of small switching margins and half-select activated errors found in Stoner-Wohlfarth MRAM. However, it is widely acknowledged that the switching fields required for toggle MRAM are substantially larger than those needed for Stoner-Wohlfarth MRAM. Previously published reports on toggle switching use large toggle start fields around 75Oe. Here we examine, both experimentally and with a single-domain model, how both the toggle start and end fields vary with free layer intrinsic anisotropy, thickness, width, aspect ratio, and interlayer exchange coupling. By optimizing these parameters, we obtain 400nm width devices with toggle start fields below 30Oe.