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The spiking neural network (SNN)-based neuromorphic hardware has been extensively studied in dynamic information processing. However, there is still a lack of training algorithms to drive or support the implementation of compact spatio-temporal neuromorphic hardware; and the existing neuromorphic hardware uses excessive on-chip memory to store parameters, which limits its neuron and synapse scale. Here, we introduce a hardware-friendly weight binarized spiking neural network (BSNN) to efficiently recognize the spatio-temporal event-based data. The neuron of the spike response model (SRM) is used in BSNN due to its rich spatio-temporal characteristics. In the training process, a surrogate gradient method is used to replace the derivative of the spike train, and the weights are binarized. Moreover, combined with the spiking characteristics of SNN (i.e., the input/output of SNN and the communications of neurons in SNN are binary spikes), it is possible to replace the hardware-expensive matrix–vector multiplication (MVM) with the hardware-friendly “Signed AND” operation during inference, which is favored for constructing compact neuromorphic hardware. The trained BSNN has competitive recognition accuracies of 99.52% and 62.1%, 97.57%, and 90.35% on the dynamic images dataset N-MNIST and DVS-CIFAR10, dynamic gestures dataset DvsGesture, and dynamic audio dataset N-TIDIGITS18, respectively, which are related to human vision or hearing. The proposed compact SNN training method paves the way for real-time dynamic information processing oriented hardware-saving and power-efficient neuromorphic hardware.

In order to accurately intercept incoming swarm targets and improve interception efficiency, the interception efficiency of various air defense equipment was studied. The paper introduces the current ways to deal with the UAV swarm, and establishes the mathematical model of different types of interception equipment; Under the premise of given interception probability, the time and cost of different interception methods are calculated respectively, and the weight distribution is used to analyze the interception efficiency of different weapons. According to the analysis process and results, the interception effectiveness of different weapons is sorted. The analysis results show that the analysis has certain practicability, which can support the development and application of air defense interception weapons and equipment to a certain extent, and has practical reference value and significance.

In recent years, the weight binarized neural network (BNN) technology has made great progress. However, neural networks with binarized inputs and binarized weights suffer from low accuracy in pattern recognition or inefficiency in hardware implementation. This work proposes a spatio-temporal binary neural network (STBNN) to solve this problem. STBNN has binary network input/output, binary neuron input/output, and binarized weights, and it integrates the computationally expensive batch normalization (BN) operation widely used in previous BNNs into the neuron threshold. STBNN can largely save computing resources and storage space while maintaining high accuracy (e.g., 98.0% on the MNIST test set). Using binary input (0 or 1) and binarized weight (±1), the product of input and weight can be realized by a 1-bit Signed AND operation instead of multiplication operation in hardware implementation, thus significantly reducing computing resources, memory requirements, and power consumption. The results show that compared with a 32-bit multi-layer perceptron (MLP)-based hardware design, the STBNN-based hardware design typically reduces these three indicators by 84.2%, 96.4%, and 96.7%, respectively. This work provides an effective method to construct hardware-friendly neural network models and a guide for designing an extremely hardware-saving neural network processor.

This paper proposes an Advanced Encryption Standard (AES) encryption technique based on memristive neural network. A memristive chaotic neural network is constructed by the use of the nonlinear characteristics of the memristor. The chaotic sequence, which is sensitive to the initial value and has good random characteristics, is used as the initial key of AES grouping to realize "one-time-one-secret" dynamic encryption. Results show that the algorithm has higher security, larger key space and stronger robustness than the conventional AES. It can effectively resist the initial key fixed and exhaustive attacks.

Neuromorphic hardware inspired by the brain has attracted much attention for its advanced information processing concept. However, implementing online learning in the neuromorphic chip is still challenging. In this paper, we present a bio-plausible online-learning spiking neural network (SNN) model for hardware implementation. The SNN consists of an input layer, an excitatory layer, and an inhibitory layer. To save resource cost and accelerate information processing speed during hardware implementation, online learning based on the spiking neural model is realized by trace-based spiking-timing-dependent plasticity (STDP). Neuron and synapse activities are digitalized, and decay behaviors of neuron and synapse parameters are realized by the bit-shift operation. After learning training set from the Modified National Institute of Standards and Technology (MNIST), the spiking neural model successfully recognizes the digits from the MNIST test set, showing the feasibility and capability of the model. The recognition accuracy increases significantly from 90.0% to 94.5% with the number of the excitatory/inhibitory neurons rising from 400 to 3,500, which provides a guide to make a trade-off between the recognition accuracy and the resource cost during hardware implementation. Encouragingly, compared to its corresponding floating-point model, the proposed model reduces the hardware resources and power consumption by 40.7% and 36.3%, respectively (under 55-nm CMOS process). Published version

In wireless devices, a transmitter normally consumes most of power due to its power amplifier (PA), especially in the applications such as radar, base station, and mobile phone. It is highly desirable to design a transmitter that can emit signals smartly, i.e., the power emission is exactly based on the emitting distance required and the target. Such a design can save huge amount of power as there are almost countless wireless devices in use currently. In this paper, an intelligent radio-frequency transmitter integrated with artificial neural network (ANN) is implemented. The intelligent transmitter consists of an ANN module, a frequency generation module, and a switch-mode PA. The integrated three-layered fully connected ANN can be offline trained to smartly classify input data according to the required power and assign the transmission channel. Furthermore, with the integrated ANN, the average power consumption of the PA is reduced to 34.3 mW, which is 46.5 % lower than PA without the ANN. With the intelligent transmitter, wireless devices can save a large amount of energy in their operations. Published version

In this paper, electrical characteristics of an HfO2-based resistive switching memory device are investigated before and after γ-ray radiation with various total ionizing doses (TIDs). The device can still function properly even if irradiated with a TID of 20 Mrad(Si). The small changes of resistance states and set/reset voltages induced by γ-ray radiation can hardly influence the proper function of the device. The γ-ray radiation does not significantly degrade both retention and endurance characteristics even after a high-TID exposure. The radiation effects on the resistive switching memory device show little dependence on the cell area. The results suggest that the HfO2-based resistive switching memory device has good γ-ray radiation-resistant capability.

With its high energy efficiency and ultra-high speed, processing-in-memory (PIM) technology is promising to enable high performance in Reservoir Computing (RC) systems. In this work, we demonstrate an RC system based on an as-fabricated PIM chip platform. The RC system extracts input into a high-dimensional space through the nonlinear characteristic and randomly connected reservoir states inside the PIM-based RC. To examine the system, nonlinear dynamic system predictions, including nonlinear auto-regressive moving average equation of order 10 driven time series, isolated spoken digit recognition task, and recognition of alphabet pronunciation, are carried out. The system saves about 50% energy and requires much fewer operations as compared with the RC system implemented with digital logic. This paves a pathway for the RC algorithm application in PIM with lower power consumption and less hardware resource required. Published version This work was supported by NSFC under Project Nos. 61774028, 92064004, and 61771097.

In this paper, a reconfigurable and scalable spiking neural network processor, containing 192 neurons and 6144 synapses, is developed. By using deep compression technique in spiking neural network chip, the amount of physical synapses can be reduced to 1/16 of that needed in the original network, while the accuracy is maintained. This compression technique can greatly reduce the number of SRAMs inside the chip as well as the power consumption of the chip. This design achieves throughput per unit area of 1.1 GSOP/( $\text{s}\!\cdot\!\text{mm}^2$ ) at 1.2 V, and energy consumed per SOP of 35 pJ. A 2-layer fully-connected spiking neural network is mapped to the chip, and thus the chip is able to realize handwritten digit recognition on MNIST with an accuracy of 91.2%.

In this paper, a 2 GHz LC-VCO with neural network (Multilayer Perceptron) has been designed in a 0.13 ţm CMOS technology. With the integrated neural network, the linearity and tuning range of the LC-VCO has been substantially improved. Compared to a conventional VCO design, the proposed technique can improve the linearity by selecting optimized bias voltages obtained from the output of the neuron network. The result shows that the tuning nonlinearity of the proposed VCO is further optimized from 0.335% to 0.254%. Published version

In this paper, an RF low noise amplifier (LNA) with self-recovery capability has been designed and implemented. A degradation model of hot carrier injection (HCI) of n-channel MOSFETs is proposed to simulate the aging process of the RF circuits, and a method for monitoring the HCI degradation in the RF circuits has been developed. Self-recovery mechanism of the LNA is triggered automatically by monitoring the HCI degradation to compensate for the HCI degradation. With the self-recovery capability, the LNA can maintain its performance under HCI stress over time. The proposed LNA has been fabricated with a 0.13μm CMOS technology and the self-recovery capability has been experimentally demonstrated. Published version

We report a p-type nickel oxide/n-type indium gallium zinc oxide (p-NiO/n-IGZO) thin film heterojunction structure for resistive switching memory application. The as-fabricated structure exhibits the normal p-n junction behaviors with good rectification characteristic. The structure is turned into a bipolar resistive switching memory by a forming process in which the p-n junction is reversely biased. The device shows good memory performances; and it has the capability of multibit storage, which can be realized by controlling the compliance current or reset stop voltage during the switching operation. The mechanisms for both the forming process and bipolar resistive switching are discussed; and the current conduction at the low- and high-resistance states are examined in terms of temperature dependence of the current-voltage characteristic of the structure. NRF (Natl Research Foundation, S’pore) ASTAR (Agency for Sci., Tech. and Research, S’pore) MOE (Min. of Education, S’pore)

This paper proposed an energy-efficient deep convolution neural networks coprocessor (DCNNs-CP) architecture for multi-object detection applications based on deep learning algorithms. The DCNNs-CP can support both convolutional layers and fully connected layers to accelerate various mobile deep learning algorithms. It also supports maximum and mean pooling operations through a separate pooling module structure. Besides, a reconfigurable activation function module supporting four nonlinear functions is also realized in this coprocessor. The DCNNs-CP chip was implemented in 55 nm CMOS process technology and occupied the 4 mm2 die area. The DCNNs-CP supports 8-bit and 16-bit fixed-point data precision and achieves a peak performance of 3.4 Tops/W at 1.2 V supply voltage and a maximum frequency of 500 MHz, represent 2.13x improvements over reported hardware accelerators. Besides, the chip achieves 0.85 Tops/W · mm2 energy efficiency per area and 34.0 Tops/W · MB energy efficiency per memory (on-chip memory), making it suitable to be integrated with the mobile devices.

Although there is a huge progress in complementary-metal-oxide-semiconductor (CMOS) technology, construction of an artificial neural network using CMOS technology to realize the functionality comparable with that of human cerebral cortex containing 1010–1011 neurons is still of great challenge. Recently, phase change memristor neuron has been proposed to realize a human-brain level neural network operating at a high speed while consuming a small amount of power and having a high integration density. Although memristor neuron can be scaled down to nanometer, integration of 1010–1011 neurons still faces many problems in circuit complexity, chip area, power consumption, etc. In this work, we propose a CMOS compatible HfO2 memristor neuron that can be well integrated with silicon circuits. A hybrid Convolutional Neural Network (CNN) based on the HfO2 memristor neuron is proposed and constructed. In the hybrid CNN, one memristive neuron can behave as multiple physical neurons based on the Time Division Multiplexing Access (TDMA) technique. Handwritten digit recognition is demonstrated in the hybrid CNN with a memristive neuron acting as 784 physical neurons. This work paves the way towards substantially shrinking the amount of neurons required in hardware and realization of more complex or even human cerebral cortex level memristive neural networks.

Synaptic memristor has attracted much attention for its potential applications in artificial neural networks (ANNs). However useful applications in real life with such memristor-based networks have seldom been reported. In this paper, an ANN based on memristors is designed to learn a multi-variable regression model with a back-propagation algorithm. A weight unit circuit based on memristor, which can be programed as an excitatory synapse or inhibitory synapse, is introduced. The weight of the electronic synapse is determined by the conductance of the memristor, and the current of the synapse follows the charge-dependent relationship. The ANN has the ability to learn from labeled samples and make predictions after online training. As an example, the ANN was used to learn a regression model of the house prices of several Boston towns in the USA and the predicted results are found to be close to the target data. Published version

Multilevel high-resistance states are achieved in TiN/HfO x /Pt resistive switching random access memory device by controlling the reset stop voltage. Impedance spectroscopy is used to study the multilevel high-resistance states. It is shown that the high-resistance states can be described with an equivalent circuit consisting of the major components $R_{s}$ , $R$ , and $C$ corresponding to the series resistance of the TiON interfacial layer, the equivalent parallel resistance, and capacitance of the leakage gap between the TiON layer and the residual conductive filament, respectively. These components show a strong dependence on the stop voltage, which can be explained in the framework of oxygen vacancy model and conductive filament concept. On the other hand, $R$ is observed to decrease with dc bias, which can be attributed to the barrier lowering effect of the Coulombic trap well in the Poole–Frenkel emission model.

The human brain is an extremely complex system of 10

Resistive switching memristor, predicted as the fourth fundamental passive circuit element (in addition to resistor, capacitor, and inductor) in the world by Leon Chua in 1971 and demonstrated by Hewlett Packard laboratory in 2008, has attracted extensive research attention for its high scalability and versatility. In this paper, we reviewed the working mechanisms and mathematical models of nanostructured resistive switching memristors, and examined various emerging applications of the memristors, including memory, analog, logic and neuromorphic applications.

Brain-inspired neuromorphic computing has attracted much attention for its advanced computing concept. However, the massive hardware cost in fully-connected architectures makes it challenging to build a large-scale neuromorphic system. In this work, we report a compact, programmable, versatile, and scalable neuromorphic architecture. To demonstrate the concept of the neuromorphic architecture, a neuromorphic system consisting of four cores is implemented on an FPGA platform. On the one hand, the neuromorphic system is extremely compact and hardware-saving. The computing block based on a simple digital leaky Integrate-and-Fire (LIF) model only costs 69 logic elements (LEs); only one physical neuron is implemented in each core, and it can be reused as hundreds of virtual neurons by time-division-multiplexing; only four 9-bit synaptic weights are assigned to each neuron, which effectively alleviates the hardware explosion in fully-connected architecture. On the other hand, the neuromorphic system is programmable and versatile, and can perform different neural network computing. The neuromorphic system mapped with a three-layer feedforward network successfully recognizes the MNIST handwritten digits with an accuracy of 96.26%, and it also effectively realizes different convolution operations which are basic computing operations in convolutional neural networks. Last but not least, each neuromorphic core has its own router module, making it convenient to scale up.

Electrical characteristics of an HfO 2 -based resistive switching memory device are investigated before and after exposure to γ ray radiation for various total ionizing doses (TIDs). The device can still function properly after radiation, showing a good anti-radiation capability. After exposure to radiation, the set and reset voltages of the device decrease very slightly, and the resistance of the low-resistance state and the high-resistance state shows little increase. The very small changes of set voltage, reset voltage and resistance after radiation do not influence the proper function of the device. The γ ray radiation does not significantly degrade both retention and endurance characteristics even after a high-TID exposure.

In this work, a synaptic transistor based on the indium gallium zinc oxide (IGZO)–aluminum oxide (Al2O3) thin film structure, which uses ultraviolet (UV) light pulses as the pre-synaptic stimulus, has been demonstrated. The synaptic transistor exhibits the behavior of synaptic plasticity like the paired-pulse facilitation. In addition, it also shows the brain's memory behaviors including the transition from short-term memory to long-term memory and the Ebbinghaus forgetting curve. The synapse-like behavior and memory behaviors of the transistor are due to the trapping and detrapping processes of the holes, which are generated by the UV pulses, at the IGZO/Al2O3 interface and/or in the Al2O3 layer. NRF (Natl Research Foundation, S’pore) ASTAR (Agency for Sci., Tech. and Research, S’pore) MOE (Min. of Education, S’pore) Published version

In this work, a flexible memory device based on resistive switching in a NiO thin film has been demonstrated. A large memory window with the resistance ratio of ∼ 10 3 between the highresistance state and the low-resistance state is observed. A memory state can be altered by either voltage pulses or a voltage sweeping. The memory window can be maintained in repetitive programming/erase cycles (at least 120 cycles have been demonstrated in the present experiment), showing a good endurance. In addition, in the time frame (10 4 s) of the retention experiment, no significant degradation in the memory window is observed, demonstrating a good retention capability.

Rapid growth of soft electronics has enabled various approaches for developing artificial skin. However, currently existing electronic skin is still facing some problems such as high fabrication complexity, high production cost, and smartness of recognizing the stimulus automatically. In this work, we report a simple, low-cost Polydimethylsiloxane (PDMS)-based smart electronic skin system, consisting of a sensor array and a data processing system. The sensor array can be easily mounted on the human body or robot hand as a result of excellent softness, stretchability, and bendability of PDMS. Signals from the sensor array are processed by a Long and Short Term Memory neural network algorithm in the data processing system. The trained data processing system can recognize four types of gestures at an accuracy of 85 ± 5%, even taking into account environmental variations including folding, curvature, tensile strength, temperature, and endurance cycles. This work proves that this type of skin can be endowed with intelligence with a proper neural network algorithm and fabricated at low cost and reduced complexity. Published version

Although synaptic behaviours of memristors have been widely demonstrated, implementation of an even simple artificial neural network is still a great challenge. In this work, we demonstrate the associative memory on the basis of a memristive Hopfield network. Different patterns can be stored into the memristive Hopfield network by tuning the resistance of the memristors, and the pre-stored patterns can be successfully retrieved directly or through some associative intermediate states, being analogous to the associative memory behaviour. Both single-associative memory and multi-associative memories can be realized with the memristive Hopfield network.

Acrylic acid (AA) was grafted to ozone treated poly (3-hydroxybutyric acid-co-3-hydroxyvaleric acid) (PHBV) membrane. The resulting membranes were further grafted with chitosan (ChS) via esterification. Afterward ChS-grafted membranes were immobilized with collagen (COL). The anti-bacterial activity of chitosan against Staphylococus aureus, Escherichia coli, and Pseudomonas aeruginosa was reserved after COL-immobilization. In addition, after COL-immobilization, the L929 fibroblasts attachment and proliferation to membranes were improved, and the protein adsorption was decreased. The results indicate that by grafting with ChS and immobilizing with COL, PHBV can not only exhibit antibacterial activity, but also improve the cell attachment as well proliferation for fibroblast.

This work studies the adhesion of clinical infecting bacteria, S. aureus and E. coli, on prosthetic polymeric materials. Membranes were prepared from polyethylene terephthalate (PET) blending at various ratios with sodium polyethylene-5-sulfoisophthalate (SPES). The membranes were characterized by measuring the contact angle, equilibrium water content, and the surface concentration of sodium sulfonate. The results show that sulfonate makes the membrane more hydrophilic. The surface properties of bacteria were determined by measuring the adhesion to n-octane (B%) and the contact angles to water and α-bromonaphthalene. For the four bacteria studied, encapsulated S. aureus was the most hydrophobic and had the highest amount of bacteria attached to the surface of SPES/PET membrane. Furthermore, the attached amount decreased with the increase of the content of SPES. Empirical correlations for predicting the attached amount from the surface properties of both polymer and bacteria were obtained from linear regression. © 2004 Wiley Periodicals, Inc. J Appl Polym Sci 91: 3587–3594, 2004

Poly(3-hydroxybutyric acid-co-3-hydroxyvaleric acid) (PHBV) membrane was treated with ozone and grafted with acrylic acid. The resulting membranes were further grafted with chitosan (CS) or chitooligosaccharide (COS) via esterification. Afterward hyaluronic acid (HA) was immobilized onto CS- or COS-grafting membranes. The antibacterial activity of CS and COS against Staphylococus aureus, Escherichia coli, and Pseudomonas aeruginosa was preserved after HA immobilization. Among them, CS-grafted PHBV membrane showed higher antibacterial activity than COS-grafted PHBV membrane. In addition, after CS- or COS-grafting, the L929 fibroblasts attachment and protein adsorption were improved, while the cell number was decrease. After immobilizing HA, the cell proliferation was promoted, the protein adsorption was decreased, and the cell attachment was slightly lower than CS- or COS-grafting PHBV.

Acrylic acid was grafted to ozone-treated poly(3-hydroxybutyric acid) (PHB) and poly(3-hydroxybutyric acid-co-3-hydroxyvaleric acid) (PHBV) membranes. The resulting membranes were further grafted with chitosan (CS) or chitooligosaccharide (COS) via esterification. These CS- or COS-grafted membranes showed antibacterial activity against Escherichia coli, Pseudomonas aeruginosa, methicilin-resistant Staphylococcus aureus (MRSA), and S. aureus. The antibacterial activity to E. coli was the highest, whereas the antibacterial activity to MRSA was the lowest among these four bacteria tested. Acrylic acid grafting can increase the biodegradability with Alcaligens faecalis, whereas CS and COS grafting can reduce the biodegradability. In addition, CS-grafted PHBV membrane showed higher antibacterial activity and lower biodegradability than COS-grafted PHBV membrane. © 2003 Wiley Periodicals, Inc. J Appl Polym Sci 12: 2797–2803, 2003

Three polyesters—poly(ethylene terephthalate), poly(2-methyl-1,3-propylene terephthalate-co-ethylene terephthalate), and poly(1,4-cyclohexylene terephthalate-co-ethylene terephthalate)—were preirradiated with 60Co-γ-rays. Then, acrylic acid and N-vinylformamide were grafted to these irradiated fibers. Fibers grafted with N-vinylformamide were further hydrolyzed with acid so that the amide groups would convert into amino groups, and they were treated with glutaraldehyde so that aldehyde groups would be introduced. Chitosan or chitooligosaccharide was then grafted to these fibers via either esterification or imine formation. Four pathogenic bacteria—methicillin-resistant Staphylococcus aureus-1 (MRSA), Staphylococcus aureus-2, Escherichid coli, and Pseudomonas aeruginosa—were tested to determine the antibacterial activities of chitosan-grafted and chitooligosaccharide-grafted fibers. The results showed that grafting chitosan via imine formation could achieve a higher surface density for amino groups and give higher antibacterial activity to those four bacteria tested. The antibacterial activity for E. coli was the highest and that for MRSA was the lowest among the four bacteria tested. © 2002 Wiley Periodicals, Inc. J Appl Polym Sci 86: 2977–2983, 2002

The human brain is an extremely complex system of 1010-1011 neurons. To construct brain-like neuromorphic hardware, the neuron unit should be implemented effectively. Here, we report a neuron transistor based on a MoS2 flake, which has summation and threshold functions similar to biological neurons and may act as a basic neuron unit in neuromorphic hardware. The neuron transistor is composed of a floating gate and two control gates. A heavily doped silicon substrate serves as the floating gate, while the two control gates are capacitively coupled with the floating gate. The neuron transistor can be well controlled by the two control gates individually or simultaneously. The drain current can be modulated by the input voltages at the control gates. While the current response of the neuron transistor has a large dependence on the magnitude of the input signal, it shows little dependence on the frequency of the input signal. To demonstrate the potential neuromorphic application of the neuron transistor, functions including abacus-like function, AND logic and OR logic are realized in the neuron transistor.

This paper presents a design of electronic synapse with Spike Time Dependent Plasticity (STDP) based on resistive memory device. With the resistive memory device whose resistance can be purposely changed, the weight of the synaptic connection between two neurons can be modified. The synapse can work according to the STDP rule, ensuring that the timing between pre and post-spikes leads to either the long term potentiation or long term depression. By using the synapse, a neural network with three neurons has been constructed to realize the STDP learning. Published version

The well-known Ebbinghaus forgetting curve, which describes how information is forgotten over time, can be emulated using a NiO-based memristor with conductance that decreases with time after the application of electrical pulses. Here, the conductance is analogous to the memory state, while each electrical pulse represents a memory stimulation or learning event. The decrease in the conductance with time depends on the stimulation parameters, including pulse height and width and the number of pulses, which emulates memory loss behavior well in that the time taken for the memory to be lost depends on how the information is learned. Published version

The switching behaviors of the resistive switching device based on Ni-rich nickel oxide thin film during the set and reset processes in the pulse voltage experiment have been examined. In the switching from a high-resistance state (HRS) to a low-resistance state (LRS) during the set process, the formation of filament is the dominant process. The switching is easier to occur with a shorter off time between pulses, indicating that heat diffusion plays an important role. On the other hand, in the switching from the LRS to the HRS during the reset process, there is a competition between the formation and deformation of filament, which is much stronger than that in the set process. The heat diffusion during the off time between pulses affects both the formation and deformation of filaments. Thus, there is no definite relationship in statistics between the off time and the occurrence of the reset switching.

A resistive switching device based on a nickel-rich nickel oxide thin film, which exhibits inherent learning and memory-loss abilities, is reported in this work. The conductance of the device gradually increases and finally saturates with the number of voltage pulses (or voltage sweepings), which is analogous to the behavior of the short-term and long-term memory in the human brain. Furthermore, the number of the voltage pulses (or sweeping cycles) required to achieve a given conductance state increases with the interval between two consecutive voltage pulses (or sweeping cycles), which is attributed to the heat diffusion in the material of the conductive filaments formed in the nickel oxide thin film. The phenomenon resembles the behavior of the human brain, i.e., forgetting starts immediately after an impression, a larger interval of the impressions leads to more memory loss, thus the memorization needs more impressions to enhance.