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The arginine-glycine-aspartic acid (RGD) motif is a cell adhesion sequence that binds to integrins. Some RGD-containing peptides promote adhesion of both embryonic stem cells and induced pluripotent stem cells (iPSCs); however, not all such RGD-containing peptides are active. In this study, we elucidated the role of RGD-neighboring sequences on iPSC adhesion using diverse synthetic peptides and recombinant proteins. Our results indicate that iPSC adhesion requires RGDX

Sparc64 XIfx, the latest high-performance computing processor, includes a 34-core processor and achieves 1.1 teraflops of peak performance. This chip is designed for massive parallel supercomputer systems that realize high performance for a wide range of real applications. As groundwork for exascale supercomputing, it has made major technological changes from the previous Sparc64 processor in the instruction set architecture, microarchitecture, memory modules, and embedded interconnect.

The 10th generation SPARC64™ processor named SPARC64 X contains 3-billion transistors on a 588mm2 die fabricated in an enhanced 28nm high-κ metal-gate (HKMG) CMOS process, with 13 layers of copper interconnect with low-κ dielectrics. More stress control, SiGe improvement and S/D optimization achieve about 10% higher performance than the standard 28nm high performance (28HP) process. SPARC64 X runs at 3.0GHz and consists of 16 cores, shared 24MB level 2 (L2) cache, four channels of 1.6GHz DDR3 controller, two ports of PCIe Gen3 controller, and five ports of system interface controller. ccNUMA is adopted as its memory system, and a cache coherence control unit for multi-chip systems with up to 64 processors is integrated into L2 cache control circuitry for lower latency and reduced area and power consumption.

Fujitsu's Sparc64 X is a processor for Unix servers that runs at a speed of 3 GHz and consists of 16 cores, a 24-Mbyte shared level-2 (L2) cache, memory controllers, I/O controllers, and system controllers for connecting multiple chips. The authors of this article enhanced the microarchitecture and introduced an extended instruction set called High-Performance Computing Arithmetic Computational Extensions (HPC-ACE), used previously in the K computer. The peak memory bandwidth is 102 Gbytes per second. These features realize extremely high-throughput performance. In addition, the authors added new functions to the processor core pipelines, which accelerate certain software tasks such as cryptographic processing. They call these functions "software on chip" (SWoC). Furthermore, they employ high-reliability technology used in mainframes to ensure stable operation of mission-critical systems. This article describes the past and current direction of the microarchitecture of the Sparc64 processor series, gives an overview of Sparc64 X, and presents results of testing the performance and power efficiency of SWoC.

The Sparc64 VIIIfx eight-core processor, developed for use in petascale computing systems, runs at speeds of up to 2 GHz and achieves a peak performance of 128 gigaflops while consuming as little as 58 watts of power. Sparc64 VIIIfx realizes a six-fold improvement in performance per watt over previous generation Sparc64 processors.

An 8-core SPARC64™ VIIIfx processor is fabricated in a 45nm CMOS process and achieves a peak performance of 128GFLOPS. Measured results show that the processor consumes only 58W of power when executing a maximum power program. Fine-grained power analysis was used to tune the micro-architecture for low power consumption, and circuit-level low-power techniques were developed. Water cooling and supply voltage adjustment contribute to power reduction at the system level.