204 results on '"Ryohei Kobayashi"'
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2. Rotary properties of hybrid F1-ATPases consisting of subunits from different species
3. Fermionic defects of topological phases and logical gates
4. Topological terms of (2+1)d flag-manifold sigma models
5. Non-local order parameters and quantum entanglement for fermionic topological field theories
6. Pin TQFT and Grassmann integral
7. On gapped boundaries for SPT phases beyond group cohomology
8. Symmetry-preserving boundary of (2+1)D fractional quantum Hall states
9. Impact of Ninjin'Yoeito on Fatigue in Patients Receiving Nab-Paclitaxel Plus Gemcitabine Therapy: A Prospective, Single-Arm, Phase II Open Label, Nonrandomized, Historically-Controlled Study
10. Anomaly constraint on chiral central charge of (2+1)d topological order
11. CHARM-SYCL & IRIS: A Tool Chain for Performance Portability on Extremely Heterogeneous Systems.
12. Improving Performance on Replica-Exchange Molecular Dynamics Simulations by Optimizing GPU Core Utilization.
13. Using Intel oneAPI for Multi-hybrid Acceleration Programming with GPU and FPGA Coupling.
14. Terpenoids and Phenylpropanoids in Ligularia duciformis, L. kongkalingensis, L. nelumbifolia, and L. limprichtii
15. Preliminary Evaluation of Kyokko for Inter-FPGA Communication Framework CIRCUS.
16. Using SYCLomatic to Migrate CUDA Code to oneAPI Adapting NVIDIA GPU.
17. Preliminary Performance Evaluation of Grace-Hopper GH200.
18. Implementation and Performance Evaluation of Collective Communications Using CIRCUS on Multiple FPGAs.
19. GPU-FPGA-accelerated Radiative Transfer Simulation with Inter-FPGA Communication.
20. CHARM-SYCL: New Unified Programming Environment for Multiple Accelerator Types.
21. OpenACC Unified Programming Environment for Multi-hybrid Acceleration with GPU and FPGA.
22. Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems.
23. Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems.
24. Multi-hetero Acceleration by GPU and FPGA for Astrophysics Simulation on oneAPI Environment.
25. Implementation and Performance Evaluation of Memory System Using Addressable Cache for HPC Applications on HBM2 Equipped FPGAs.
26. Accelerating Radiative Transfer Simulation on NVIDIA GPUs with OpenACC.
27. An FPGA-based Accelerator for Regular Path Queries over Edge-labeled Graphs.
28. Performance Evaluation on GPU-FPGA Accelerated Computing Considering Interconnections between Accelerators.
29. Performance improvement by enhancing spatial parallelism on FPGA for HPC applications.
30. An Open-source FPGA Library for Data Sorting.
31. HBM2 Memory System for HPC Applications on an FPGA.
32. Performance Evaluation of OpenCL-Enabled Inter-FPGA Optical Link Communication Framework CIRCUS and SMI.
33. An efficient RTL buffering scheme for an FPGA-accelerated simulation of diffuse radiative transfer.
34. A Sorting Library for FPGA Implementation in OpenCL Programming.
35. Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA.
36. Accelerating Radiative Transfer Simulation with GPU-FPGA Cooperative Computation.
37. OpenCL-enabled Parallel Raytracing for Astrophysical Application on Multiple FPGAs with Optical Links.
38. Parallel Processing on FPGA Combining Computation and Communication in OpenCL Programming.
39. GPU-FPGA Heterogeneous Computing with OpenCL-Enabled Direct Memory Access.
40. Multi-Hybrid Accelerated Simulation by GPU and FPGA on Radiative Transfer Simulation in Astrophysics.
41. Cygnus - World First Multihybrid Accelerated Cluster with GPU and FPGA Coupling.
42. OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing.
43. Accelerating Space Radiative Transfer on FPGA using OpenCL.
44. Toward OpenACC-enabled GPU-FPGA Accelerated Computing.
45. ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment.
46. Development of a high-sensitivity and portable cell using Helmholtz resonance for noninvasive blood glucose-level measurement based on photoacoustic spectroscopy.
47. A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism.
48. A Challenge of Portable and High-Speed FPGA Accelerator.
49. Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research.
50. FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems.
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