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3. Design of asynchronous microprocessor for power proportionality

Author

Rykunov, Maxim

Subjects
621.39
Abstract

Microprocessors continue to get exponentially cheaper for end users following Moore’s law, while the costs involved in their design keep growing, also at an exponential rate. The reason is the ever increasing complexity of processors, which modern EDA tools struggle to keep up with. This makes further scaling for performance subject to a high risk in the reliability of the system. To keep this risk low, yet improve the performance, CPU designers try to optimise various parts of the processor. Instruction Set Architecture (ISA) is a significant part of the whole processor design flow, whose optimal design for a particular combination of available hardware resources and software requirements is crucial for building processors with high performance and efficient energy utilisation. This is a challenging task involving a lot of heuristics and high-level design decisions. Another issue impacting CPU reliability is continuous scaling for power consumption. For the last decades CPU designers have been mainly focused on improving performance, but “keeping energy and power consumption in mind”. The consequence of this was a development of energy-efficient systems, where energy was considered as a resource whose consumption should be optimised. As CMOS technology was progressing, with feature size decreasing and power delivered to circuit components becoming less stable, the energy resource turned from an optimisation criterion into a constraint, sometimes a critical one. At this point power proportionality becomes one of the most important aspects in system design. Developing methods and techniques which will address the problem of designing a power-proportional microprocessor, capable to adapt to varying operating conditions (such as low or even unstable voltage levels) and application requirements in the runtime, is one of today’s grand challenges. In this thesis this challenge is addressed by proposing a new design flow for the development of an ISA for microprocessors, which can be altered to suit a particular hardware platform or a specific operating mode. This flow uses an expressive and powerful formalism for the specification of processor instruction sets called the Conditional Partial Order Graph (CPOG). The CPOG model captures large sets of behavioural scenarios for a microarchitectural level in a computationally efficient form amenable to formal transformations for synthesis, verification and automated derivation of asynchronous hardware for the CPU microcontrol. The feasibility of the methodology, novel design flow and a number of optimisation techniques was proven in a full size asynchronous Intel 8051 microprocessor and its demonstrator silicon. The chip showed the ability to work in a wide range of operating voltage and environmental conditions. Depending on application requirements and power budget our ASIC supports several operating modes: one optimised for energy consumption and the other one for performance. This was achieved by extending a traditional datapath structure with an auxiliary control layer for adaptable and fault tolerant operation. These and other optimisations resulted in a reconfigurable and adaptable implementation, which was proven by measurements, analysis and evaluation of the chip.

Published
2014

8. Programmable Systems for Intelligence in Automobiles (PRYSTINE): Final results after Year 3

Author

Druml, Norbert, primary, Ryabokon, Anna, additional, Schorn, Rupert, additional, Koszescha, Jochen, additional, Ozols, Kaspars, additional, Levinskis, Aleksandrs, additional, Novickis, Rihards, additional, Nigussie, Ethiopia, additional, Isoaho, Jouni, additional, Solmaz, Selim, additional, Stettinger, Georg, additional, Diaz, Sergio, additional, Marcano, Mauricio, additional, Villagra, Jorge, additional, Medina, Juan, additional, Schwarz, Martina, additional, Artunedo, Antonio, additional, Comi, Mauro, additional, Beekelaar, Rutger, additional, Ozcelik, Onur, additional, Tasdelen, Elif Aksu, additional, Gurbuz, Yesim, additional, Saijets, Jan, additional, Kyynarainen, Jukka, additional, Morits, Dmitry, additional, Debaillie, Bjorn, additional, Rykunov, Maxim, additional, Escamilla, Joan, additional, Vanne, Jarno, additional, Korhonen, Tomi, additional, Holma, Kalle, additional, Matzhold, Eva-Maria, additional, Novara, Carlo, additional, Tango, Fabio, additional, Burgio, Paolo, additional, Calafiore, Giuseppe, additional, Karimshoushtari, Milad, additional, Boulay, Emilie, additional, Dhaens, Miguel, additional, Praet, Kylian, additional, Zwijnenberg, Han, additional, Palm, Henri, additional, Ortega, David Aledo, additional, Kalali, Ercan, additional, Pensala, Tuomas, additional, Kyytinen, Arto, additional, Larsen, Morten, additional, Veledar, Omar, additional, Macher, Georg, additional, Lafer, Michael, additional, Giraudi, Lorenzo, additional, Reckenzaun, Jakob, additional, Hammer, Daniel, additional, Mohan, Naveen, additional, Schmid, Josef, additional, Hos, Alfred, additional, Ophir, Shai, additional, Dubey, Anand, additional, Fuchs, Jonas, additional, Lubke, Maximilian, additional, Anghel, Andrei, additional, Ristea, Nicolae-Catalin, additional, Torngren, Martin, additional, Musralina, Alua, additional, Harter, Marlene, additional, Jose, Joseena Memadathil, additional, and Dimitrakopoulos, George, additional

Published
2021
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9. Radar fusion for multipath mitigation in indoor environments

Author

Pocoma Copa, Evert Ismael, Aziz, Kheireddine, Rykunov, Maxim, De Greef, Eddy, Bourdoux, André, Horlin, François, Pocoma Copa, Evert Ismael, Aziz, Kheireddine, Rykunov, Maxim, De Greef, Eddy, Bourdoux, André, and Horlin, François

Abstract

One of the main challenges of radar-based localization applications in indoor environments is the presence of strong multipath. When the radar bandwidth is large enough, multipath components can be resolved in range but they result in unwanted ghost targets. We propose a novel multipath mitigation approach that exploits the fact that multipaths are highly dependent on the scene geometry. The multipath mitigation approach discards the ghost targets based on the fused information of multiple radars located at different positions in the scene. For such radar fusion, the output of the radar signal processing chain is translated into the world coordinate system that is common for all the radars. We propose a radar alignment approach to estimate the translation and rotation parameters from radar to world coordinate system and vice versa. Our multipath mitigation method is combined with an unscented Kalman filter to improve the localization accuracy. We demonstrate the effectiveness of our complete approach with a real experiment using two radars to detect and track a target in a room with severe multipath., SCOPUS: cp.p, info:eu-repo/semantics/published

Published
2020

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