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Shortening the startup time of a crystal oscillator is critical in improving the energy efficiency of the Internet of Things (IoT) sensor nodes. This article presents an investigative study on the application of adaptive chirping using zero-phase cross-detection to reduce the startup time of a crystal oscillator that is robust to voltage, temperature and even process variations without any costly trimming. Post-layout simulations on a 38.4 MHz crystal resonator with 1.0 V supply and 65-nm CMOS process confirms the feasibility of this approach and its ability to effectively reduce the startup time by correcting both phase and frequency mismatches. The results showcase the promising potential of zero-phase adaptive chirp as a viable variation-tolerant technique allowing for a high frequency mismatch tolerance of $1.1\times 10 ^{6}$ ppm- $\Delta f$ .

The increasing demand for wireless Internet of Things (IoT) calls for power efficient RF energy harvesting approach. The current dominant single-band RF energy harvesting front-end system restricts itself to a single frequency, which is at the risk of ineffective operation when the harvesting frequency is unavailable. This paper reviews and explores the alternative approach of a multiband RF energy-harvesting front-end system. It covers all essential circuitry of a multiband RF energy harvesting front-end system, starting from the recent RF surveys which investigate the typical, usable, and high-strength RF input, to the overview of the state-of-the-art antenna, impedance matching network (IMN), and RF-DC rectifier. The recent advancement of the multiple RF input harvesting abilities, reflection loss minimization, and performance improvement are comprehensively reviewed for different operating conditions, and this review also presents the advantages and disadvantages of the different circuit architecture combinations for multiband RF energy harvesting front-end systems. In summary, this review aims to fill the research gap in the further advancement of multiband RF energy harvesting towards enhancing its performance through optimal circuit integration of the front-end system.

The advancement in Power Management Integrated Circuit (PMIC) has driven the dc-dc conversion technology into a System-on-Chip (SoC) solutions, leveraging CMOS technology scaling from 180nm to 22nm and on-chip passive element integration. Concurrently, as the applications demand smaller form factor solution towards device portability with optimized power qualities, switched-capacitor-inductor hybrid architectures with fully-integrated passives have become a popular choice for a compact and high efficiency converter solution, in contrast to bulky and discrete component based alternatives. This article reviews the latest advancements in hybrid dc-dc topologies, specifically for low-power applications to address the downsides such as charge sharing loss, high current ripple, limited conversion ratio, low-power density, and efficiency. An overview of capacitor and inductor technology is discussed in terms of on-chip parasitic losses, and miniaturization. A comprehensive comparison in the state-of-the-art hybrid dc-dc converter work is tabulated with power density and efficiency as the primary performance metrics, highlighting their operability in low-power applications. Moreover, a discussion is included with quantified benchmarks to justify the viability of converters, along with the future recommendation of realizing ultra-high switching frequency for smaller footprint inductor and design approach to resolve the current tradeoff bottlenecks.

A rooftop photovoltaic (PV) system is a significant solution of building-integrated centralized generation in the low-voltage (LV) DC grid. The drilling-free rooftop PV-inductive wireless power transfer (PV-IWPT) system for the LVDC grid can reduce the installation and post-maintenance costs, with the elimination of physical cable connections and preventing breaking of thermal bridge and rain penetration between the rooftop and the inside of the building. Moreover, it has inherent isolation properties between the input and the output terminals. However, it is challenging for the PV-IWPT system to simultaneously achieve the maximum power point tracking (MPPT) for the PV panels and the maximum efficiency point tracking (MEPT) for the system even under diverse irradiance conditions. In this paper, we propose an efficient PV-IWPT system, which consists of a series-series IWPT converter, driven by the PV panels and loaded by the LVDC grid directly. Moreover, we apply in the proposed system a particle swarm optimization with an auxiliary Perturb and Observe (P&O) algorithm and a load matching method without wireless feedback communication to realize MPPT and MEPT in the overall PV-IWPT system simultaneously. Finally, we analyze theoretically and verify experimentally the proposed PV-IWPT system in a 500-W experimental platform under different irradiance conditions.

This paper proposes a fully-integrated dual-band CMOS RF energy harvesting (RFEH) front-end with an adaptive frequency selector that can select between two harvesting frequencies of 1.9 GHz and 2.4 GHz. The RFEH front end includes two pairs of on-chip LC networks and rectifiers that convert the harvested RF power into a usable DC voltage. An internal control logic circuit, powered by an auxiliary path, selects the input harvesting frequency band with a higher power output to the load. The proposed dual-band adaptive frequency selection RFEH system achieves a peak PCE of 40% and 32% at 1.9 GHz and 2.4 GHz, respectively.

Low-dropout (LDO) voltage regulator has fascinated industry professionals and academia for the past few decades, and this trend is expected to continue in the coming years. The high demand for a stable linear regulator architecture that performs well in systems-on-chip (SoC) power management integrated circuits (PMICs) is a key factor driving innovation with different complementary metal-oxide-semiconductor (CMOS) technologies. Yet, there are several performance parameter trade-offs to be considered, such as transient response, output ripple, area, power efficiency, supply voltage range, and current efficiency in the current LDO design architecture. All these parameter trade-offs become more severe during the back-end CMOS processes with additional limitations, for example, channel length modulation, stress sensitivity, and power leakage, among others. Therefore, this paper presents an overview and comparison of various digital LDO (DLDO) topologies, functionalities, and performance specifications, which can serve as a virtual study or reference for others.

This work proposes a CMOS reconfigurable charge pump (CP) for a low-voltage energy harvesting system. It utilizes the low effective resistance from the parallel CP to enhance its power conversion efficiency (PCE). The CP exhibits an adaptive configuration with different stages depending on the input voltage, changing its voltage conversion ratio (VCR) to limit the output voltage under 1.8-V. Additionally, this work develops a novel dynamic source-fed oscillator that modulates the oscillating frequency by utilizing a dynamic source for the ring-voltage controlled oscillator (RVCO). The independent source from the RVCO and the clock-generating units from the proposed technique permit the implementation of frequency modulation without affecting the clock amplitude. Fabricated in 65-nm CMOS, the proposed prototype measures 62% peak PCE with an input voltage range of 0.26-V to 0.64-V.

This paper reports an ultra-low-voltage (ULV) single-crystal oscillator-timer (XO-Timer) for sub-0.5 V Bluetooth low-energy (BLE) radios that aims for self-powering by harvesting the ambient energies. Specifically, we tailor an on-chip micropower manager $(\mu $ PM) to customize the voltage and current budgets for each sub-function of the XO-Timer. Such $\mu $ PM shows a high power efficiency by introducing a 3-stage cascaded structure and a single voltage-regulation loop; they together uphold the performance of the XO-Timer amid supply-voltage and temperature variations. The core amplifier of the XO-Timer is ULV-enabled, and is reconfigurable (i.e., 1-stage and 3-stage gm) to balance between the power budget and performance under the high-performance mode (HPM) and low-power mode (LPM). Fabricated in 28-nm CMOS, the XO-Timer in HPM generates a 16-MHz clock with a power of $24.3 ~\mu \text{W}$ , and a phase noise of −133.8 dBc/Hz at 1-kHz offset, resulting in a Figure-of-Merit (FoM1) of −236 dBc/Hz. In the LPM, the XO-Timer delivers a 32.258-kHz clock while consuming $11.4 ~\mu \text{W}$ . The sleep-timer FoM2 is $14.8 ~\mu \text{W}$ and the Allan deviation is 35.1 ppb, achieving the lowest supply voltage (0.25 V) not only for a dual-mode XO-Timer but also for a MHz-range XO.

Abstract This letter presents two transient enhancement techniques for multi‐path switched‐capacitor‐inductor (MP‐SCI) hybrid DC–DC converters to eliminate the line‐transient‐induced voltage coupling to the converter output. Since the existing input‐feedforward method is hard to apply to the MP‐SCI converter, the proposed techniques tackle the intrinsic hard‐charging property with the MP‐SCI topology, preventing the line‐coupling current through topology operation reconfiguration and power‐switch modulation. The proposed controller also achieves adaptive line‐transition detection and automatic flying‐capacitor voltage balancing, ensuring a fast line regulation feature. Implemented with an MP‐SCI topology for a 9 to 14 V‐input to 5 V‐output conversion, the proposed control techniques provide an output (VOUT) overshoot and undershoot as low as 0.5% of the output DC level under a 3‐V input voltage step. From the simulation, the corresponding output variation reduction can be more than 94% when compared with the existing MP‐SCI operations. Besides, the proposed controller is compatible with a voltage‐mode (VM) V2 pulse‐width modulation (PWM) function, achieving a fast load‐transient recovery in six switching cycles and a VOUT variation of 75 mV at a 5 V DC level under a 0‐to‐3 A load step. The peak conversion efficiency can be as high as 95.5%, and the targeted load current delivery is up to 3 A.

Abstract This letter presents an automatic power‐stage implementation and optimization methodology for fully‐integrated reconfigurable switched‐capacitor (SC) DC‐DC converters with fine‐grained voltage conversion ratios (VCRs). The proposed technique resolves the design challenge of a simultaneous realization of full capacitance utilization, optimal sub‐cell sizing ratio, and implementation complexity reduction. It is based on the proposed partitioning algorithms and attains a significant sub‐cell number reduction, particularly for finer‐grained VCR designs, saving the power‐stage area overhead. With a given set of VCRs and hardware constraints, the proposed methodology can generate a specific power‐stage partitioning solution, including the total number and sizing ratio for the power stage sub‐cells, ensuring an optimal power‐stage conduction loss property under a given on‐chip capacitance area. The proposed methodology is applicable to both linear and binary types of SC converters. Compared with the advanced works, the proposed method realizes the number of sub‐capacitors reduction over 50% under the same VCRs. Meanwhile, over 90% of the sub‐cells can be eliminated for linear‐type SC converters with a VCR range of 10:1–2:1, theoretically.

ABSTRACT: This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Particularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analytically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of different circuit techniques to optimize the clock performance under different scenarios.

Driven by the momentum toward compact and low-power Internet-of-Things (IoT) systems, the research on fully-integrated and energy-efficient kHz-to-MHz timers increased explosively. This article examines recent publications on timers and classifies them into two major categories: open-loop-based and close-loop-based timers. Upon introducing the basic parameters for characterizing a timer, we perform an extensive investigation to gain insights into recent state-of-the-art works. We also discuss in detail the comparison between the two classes of timers. With the aid of the state-of-the-art, we present a comprehensive review from multiple perspectives, such as Energy Efficiency, Temperature Coefficient, Temperature Range, Figure-of-Merit, etc.

Conventional SC-based charge pump with fixed conversion ratio is predominantly adopted in energy harvesting (EH) systems, which becomes a bottleneck for attaining high power conversion efficiency (PCE) with wide dynamic range (WDR). This article reviews and explores the SC-based reconfigurable charge pump (RCP) as an alternative voltage-boosting element for the EH system. An overview of the RCP structure is established, followed by a comprehensive review of CP reconfigurable topologies along with state-of-art architecture. Design consideration of the RCP in terms of dynamic range, PCE, and VCE is provided to give a clear insight into the future development of RCP architecture for the EH system.

Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply rejection (PSR). However, the preference of achieving high performance in terms of load transient, high PSR, good load and line regulation, while maintaining a low quiescent current and low dropout voltage for high efficiency, remains the key challenge in ALDO design. For operation with a low quiescent current, the bandwidth is reduced due to low transconductance, resulting in the limited gate driving capabilities in terms of charging and discharging the large gate capacitance of the pass or output transistor. In addition, the preference for system-on-chip design in the absence of large off-chip capacitors arises stability issues. In this paper, recent reported state-of-the-art architectures for ALDOs are revisited and reviewed. The performance of these ALDOs is compared and their applications are investigated.

Real-time pH control on-chip is a crucial factor for cell-based experiments in microfluidics, yet difficult to realize. In this paper, we present a flexible pH regulator on a digital microfluidic (DMF) platform. The pico-dosing technology, which can generate and transfer satellite droplets, is presented to deliver alkali/acid into the sample solution to change the pH value of the sample. An image analysis method based on ImageJ is developed to calculate the delivered volume and an on-chip colorimetric method is proposed to determine the pH value of the sample solution containing the acid-base indicator. The calculated pH values show consistency with the measured ones. Our approach makes the real-time pH control of the on-chip biological experiment more easy to control and flexible.

Abstract Wireless power transfer systems demand a regulating transmitter (TX) for global loop control and also a regulating receiver (RX) for its local loop. This design broadens the TX output power range, by merging a switched capacitor (SC) circuit with only 3 switches and 1 flying capacitor to boost the output power of the Class‐D power amplifier. In addition, the transmitting power can be regulated by the duty ratio of the SC, improving the end‐to‐end power transfer efficiency under different load conditions. Moreover, the system obtains fast load transient response, with the help of a light‐to‐heavy load transient enhancement scheme in the TX and the hysteretic control in the RX. Designed in a 0.18‐μm BCD process, this work achieves 3.1 W maximum RX output power, 67.6% peak total efficiency, and 50 μs response time during the light‐to‐heavy load transient simulation.

This paper reports two variable-gain amplifiers (VGAs) featuring a new pseudo-current-steering gain-tuning technique. In the first VGA (VGA-I), a single-voltage-controlled dual-branch current mirror is developed as a standalone gain control block. In the second VGA (VGA-II), two NMOS transistors, which are biased by a tunable voltage, are integrated into a conventional common-source amplifier to steer away from a part of the total current. Meanwhile, the theoretical analysis is developed to reveal the mechanism of different gain tuning. Fabricated in a 40-nm CMOS process, VGA-I (VGA-II) occupies a tiny area of 0.03 mm2 (0.024 mm2) and consumes 22 mW (20 mW). Measured over a gain range of >64 dB, the -3-dB bandwidth of VGA-I (VGA-II) is 9 GHz (6.6 GHz). For the time-domain tests, VGA-I (VGA-II) exhibits a jitter of 40 ps (30 ps), under a 27-1 PRBS input at 12 Gb/s. Their power efficiencies (1.83 and 1.67 pJ/bit) compare favorably with state-of-the-art.

This paper presents a dual-antenna energy harvesting (EH) system using full-energy extraction (FEE) to reduce the buffer capacitor requirement and improve the input power response speed. Instead of using large buffer capacitors (in the order of $\mu \text{F}$ ) at the rectifier output, the proposed FEE technique can efficiently harvest the incoming 915MHz radio-frequency (RF) energy using only a 1-nF capacitor per channel, while reducing the operating frequency of the subsequent DC-DC converter for power loss minimization. The two most popular RF rectifiers are investigated to relax the energy extraction degradation due to impedance mismatch. The boost DC-DC converter combines the harvested energy from the dual-inputs through the FEE controller. Fabricated in standard 0.18- $\mu \text{m}$ CMOS and wire-bonded on an FR4 PCB, the dual-antenna EH system with the DC-DC converter operating typically at 6.25kHz demonstrates a measured peak system efficiency of 75.2% at an output power of $22.6~\mu \text{W}$ using only two 1-nF buffer capacitors at 1- $\mu \text{F}$ load. With a significant buffer size reduction than prior art at similar efficiency/power level, a short startup time of ~ 45ms is achieved when the output rises from 0 to 1 V at $15.5~\mu \text{W}$ total rectifier output power, corresponding to 90% startup time reduction over the conventional approach.

High precision data acquisition requires very-high-resolution Analog-to-digital converters (ADC) for kHz speed or to keep a relatively high resolution for wider bandwidth (BW) around the MHz range. Although widely used, noise-shaping (NS) in ADCs offers a high-resolution characteristic, but obtaining good power efficiency and compact die area is still challenging. Recent literature showed promising progress by utilizing hybrid Discrete-Time (DT) NS-ADCs with measured silicon results. This paper focuses its analysis and discussion on two important trending classes: hybrid Incremental ADCs (I-ADC) and hybrid Time-interleaved (TI) NS-ADCs. Furthermore, this paper presents a review and addresses the benefits of those hybrid architectures.

This article presents a 16-channel 5 GS/s time-interleaved (TI) SAR ADC for a direct-sampling receiver that employs a digital-mixing background timing mismatch calibration to compensate for timing-skew errors. It uses a first-order approximation to obtain the derivative of the autocorrelation of the input signal, subsequently used to evaluate the explicit amount of the timing-skew. Therefore, this allows a digital background calibration of the timing-skew, avoiding extra analog circuits. The proposed 16-channel TI ADC uses a splitting-combined monotonic DAC switching method for the individual SAR channel to achieve a trade-off of simple switching and small common-mode voltage variation of the comparator. The prototype, implemented in 28 nm CMOS, reaches a 48.5/47.8 dB SNDR with an input signal of 2.38/4.0 GHz after the proposed background timing mismatch calibration, respectively. Furthermore, the ADC core's power consumption is 29 mW sampling at 5 GS/s, with a Walden FoM of 26.7 fJ/conv.-step and a Schreier FoM of 157.9 dB.

This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency. Unlike the typical type-II single-loop PLL using a tri-state phase-frequency detector (PFD) plus a charge pump (CP) that has several limits in high-speed operation, our proposed PLL features a dual-loop scheme to enhance its performance and operating speed at low power. Specifically, we propose a dynamic frequency detector (FD) and a phase detector (PD) in conjunction with voltage-to-current converters (VICs) to avoid the typical current-mode-logic (CML) circuitry for static power reduction. Prototyped in 65-nm CMOS process, the entire PLL dissipates 10.6 mW, of which the dynamic FD and PD merely consume 0.28 mW. The integrated jitter is 415.6 fsrms (10 kHz to 100 MHz) and the reference spur level is -53 dBc at a 26.4-GHz output.

This paper proposes a 2.4-GHz fully-integrated single-frequency multi-channel RF energy harvesting (RFEH) system with increased harvested power density. The RFEH can produce an output power of ~423-μW in harvesting ambient RF energy. The front-end consists of an on-chip impedance matching network with a stacked rectifier concurrently matched to a 50 Ω input source. The circuit mitigates the “dead-zone” by enhancing the pumping efficiency, achieved through the increase of Vgs drivability of the proposed internal gate boosting 6-stage low-input voltage charge pump and the 5-stage shared-auxiliary-biasing ring-voltage-controlled-oscillator (VCO) integrated to improve the start-up. The RFEH system, simulated in 180-nm complementary metal–oxide–semiconductor (CMOS), occupies an active area of 1.02 mm2. Post-layout simulations show a peak power conversion efficiency(PCE) of 21.15%, driving a 3.3-kΩ load at an input power of 0 dBm and sensitivity of −14.1 dBm corresponding to an output voltage, Vout,RFEH of 1.25 V.

The emergence of the novel severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2), a zoonotic pathogen, has led to the outbreak of coronavirus disease 2019 (COVID-19) pandemic and brought serious threats to public health worldwide. The gold standard method for SARS-CoV-2 detection requires both reverse transcription (RT) of the virus RNA to cDNA and then polymerase chain reaction (PCR) for the cDNA amplification, which involves multiple enzymes, multiple reactions and a complicated assay optimization process. Here, we developed a duplex-specific nuclease (DSN)-based signal amplification method for SARS-CoV-2 detection directly from the virus RNA utilizing two specific DNA probes. These specific DNA probes can hybridize to the target RNA at different locations in the nucleocapsid protein gene (N gene) of SARS-CoV-2 to form a DNA/RNA heteroduplex. DSN cleaves the DNA probe to release fluorescence, while leaving the RNA strand intact to be bound to another available probe molecule for further cleavage and fluorescent signal amplification. The optimized DSN amount, incubation temperature and incubation time were investigated in this work. Proof-of-principle SARS-CoV-2 detection was demonstrated with a detection sensitivity of 500 pM virus RNA. This simple, rapid, and direct RNA detection method is expected to provide a complementary method for the detection of viruses mutated at the PCR primer-binding regions for a more precise detection.

Digital Microfluidics (DMF) is a promising technology for biological/chemical micro-reactions due to its distinct droplet manageability via electronic automation, but the limited velocity of droplet transportation has hindered DMF from utilization in high throughput applications. In this paper, by adaptively fitting the actuation voltages to the dynamic motions of droplet movement under real-time feedback monitoring, two control-engaged electrode-driving techniques: Natural Discharge after Pulse (NDAP) and Cooperative Electrodes (CE) are proposed. They together lead to, for the first time, enhanced droplet velocity with lower root mean square voltage value.