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Decrease in size of IP cores, the Network-On-Chip (NOC), which is used to interconnect them, becomes more complex. NOC employ Network Interface (NI), routers and links. Chip process technology is shrinking day by day resulting in design complexities. This rises the chances of NOC becoming faulty and corrupting the packets transmitted through it. Further NOC has great influence on the complete system performance. Despite the fact that the NOC outperforms the traditional bus based interconnects, NOC faces problems with the usage of router pipeline stages. Generic pipelined router consists of Routing Computation (RC) stage, Virtual channel Allocator (VA) stage, Switch Allocator (SA) stage and CrossBar (CB) stage. These routers are more liable to hard faults and soft-errors. Hence, incorporation of an error tolerant technique to the pipeline stages is required. However, these results in area, power and delay overhead. In this paper, we proposes Route-On-Fly NOC router architecture with Soft-error tolerance (ROFNS), an optimized pipeline router with tolerance to soft errors. In addition, optimized VA stage to achieve overall reduction in area and delay penalty is also proposed. Implementation results show that there is 70%, 3% and 16% reduction in area, power and delay respectively when compared to Soft-error Tolerant NOC Router (STNR).

The paper presents the exploration of the architecture and the transient fault effect analysis of heterogeneous NoC. Here we are analyzing various parameters such as throughput, latency and sink bandwidth considering traffic conditions, number of virtual channels, number of cores in router design Additionally, asynchronous architecture is also checked for glitch fault effect tolerance. With these analyses, ASRD(Asynchronous Router Design) is showing better results in terms of throughput and latency compared to SRD(Synchronous Router Design). It is also found to be with inherent fault tolerant potential because of handshaking alerts and about half of the infused faults get converted into new qualities before transforming into mistakes. Finally, our paper concludes from the result that asynchronous router design is more fault tolerable with proposed architecture.

The proposed work demonstrates a novel flow control mechanism that brings the flexibility to route every flit of a packet independently, alleviating the network congestion more efficiently in Virtual Channel (VC) based NoC routing. A 100% buffer utilization is achieved by putting an end to the overhead of VC arbitration. The modified router design comes with a 20% area and 4.73% energy saving on the generic one. Packet Latency improvement of 35 -78 %, 27 - 68%, and 45 - 62% is observed over the mesh, torus, and flattened butterfly topologies respectively under uniform random traffic. The average packet drop rate is reduced by a minimum of 28% across the above topologies.

We demonstrate that the non-Hermitian Hamiltonian approach can be used as a universal tool to design and describe a performance of single photon quantum electrodynamical circuits (cQED). As an example of the validity of this method, we calculate a novel six port quantum router, constructed from four qubits and three open waveguides. We have obtained analytical expressions, which describe the transmission and reflection coefficients of a single photon in general form taking into account the spread qubit&rsquo, s parameters. We show that, due to naturally derived interferences, in situ tuning the probability of photon detection in desired ports.

The art of carving or engraving ornament is the image with certain parts, usually concave, convex or flat, patterned and has a motive. Sculpture can be formed pictures on wood, acrylic, or other materials. In making this product a design researcher perform analysis or potential problems that occur with experiments in doing a good carving designs are done by hand or automatically The definition is a prototype assessment products through on eor more dimensions of concern. In the process of making utensils or equipment requires some work benchesare wont to do in the workshop in general. After the finished product made testing will be conducted experiments in order to know the performance of the products. Testing is carried out using a sample design engraving. The concept of design and manufacture of the products is a bigpart of engineering Activities. This activity starts with he obtained perceptions about human needs, which are then followed by the concept, then designing, developing and refining the product, ending with the manufacture of the product

An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh topology-based NOC architecture are designed. The Priority –Arbiter based Router design includes Input registers, Priority arbiter, and XY- Routing algorithm. The Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim 6.5f. The implementation is done by Artix-7 FPGA device, and the physically debugging of the NOC 2X2 Router design is verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum operating frequency. The comparison of the Priority-Arbiter based Router is made concerning previous similar architecture with improvements.

Purpose – The purpose of this paper is to provide the method and system to conduct online measurement and the characterization of temperature during printed circuit board (PCB) routing process as well as the optimization of router design based on the investigation of routing temperature. Design/methodology/approach – The background of this research is introduced first. Then the method to measure the routing temperature on-line by using an infrared camera is presented. The routing process is characterized by investigating the routing temperature. Tool design optimization is conducted based on the temperature in processing PCB with aluminum substrate. Finally the concluding remarks of this research are presented. Findings – The routing temperature can be accurately measured by an infrared camera. Routing temperature is sensitive to properties of PCB, types of router and routing parameters. Very high temperature is experienced if non-appropriate routers are used to process board with aluminum substrate. It is demonstrated by the experiments that two fluted tool, three fluted tool and coated tool with three flutes are suitable for aluminum substrate processing by considering the low temperature and the nice surface finish. Originality/value – The paper highlights the key points to measure the routing temperature on-line by an infrared camera and characterize the routing process and optimize the tool design by investigating the measured temperature as well.

The GR718B is a standalone, radiation tolerant, 18x-port SpaceWire router, enhanced with support for 64 interrupts, SpaceWire-D and SpaceWire standard revision 1. A brief overview of the design background of this device is provided herein. The main design features of the GR718B are also described in this paper. A short summary of the screening and qualification flows for space qualification of the GR718B is given herein. GR718B prototypes have already passed functional and electrical verification and the first flight lot of GR718B is now in its final stage of space qualification. The main outcome the Single Event Effects testing of the GR718B are given here and support the choice of radiation hardening features selected for the design of this device.

Owing to its simple router design and insensitivity to the message distance, wormhole switching has been employed not only in networks for contemporary multicomputers but also, in networks for clusters of workstations, and more recently in networks for systems-on-chips. Although analytical performance models for wormhole-switched networks have been widely reported in the literature, most of these models have assumed no (or negligible) buffers at a given router in order to ease the derivation of the model. In this paper, we propose a new simple and yet accurate model to capture the effects of finite buffers on the performance of wormhole-switched networks. Simulation experiments demonstrate the validity of the suggested model under various operating conditions.

Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature. By varying junction temperature the value of leakage is observed and its effect on total power dissipated is also obtained. This research is made by keeping output load at value 50.The result is also obtained at different frequencies i.e. at 10MHz, 0.1GHz and 1GHz. Different values of output power at observed and reduction the power is calculated accordingly. So this project gives an overview to make the router efficient by varying junction temperature. KeywordsFPGA, Power, Router, Junction Temperature, Energy Efficiency

Communication is the major aspect that plays an important role in success of any organization. Information in the same way is another aspect as to have communication data or information is must. So with the help of computer networks it is possible to build an environment of communication and information. Router is main component of computer networks is an intelligent device uses to transfer data packets between various computer networks. Router must consume low power to perform its work in an efficient manner. To achieve the same the work has been done to make a FPGA based low power design using different standards of HSTL.

In this paper, a novel system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic characteristics of the target application and the total budget of the available buffering space, the proposed algorithm automatically assigns the buffer depth for each input channel, in different routers across the chip, such that the overall performance is maximized. This is in deep contrast with the uniform assignment of buffering resources (currently used in NoC design), which can significantly degrade the overall system performance. Indeed, the experimental results show that while the proposed algorithm is very fast, significant performance improvements can be achieved compared to the uniform buffer allocation. For instance, for a complex audio/video application, about 80% savings in buffering resources, can be achieved by smart buffer allocation using the proposed algorithm

Network on chip (NoC) has been proposed over bus to address the communicational prerequisite of highly dense multi-core systems. NoCs with buffer-less routers gain popularity due to simplicity in the router design, low power consumption and less chip area. The state of the art of deflection router DeBAR employs side buffers instead of input port buffers, that can accommodate one among the deflected flit per router per cycle. In this paper we propose deflection history as a priority metrics for flit selection. We, modify the primitive DeBAR design, and propose priority based deflection based adaptive router (PBDeBAR) that make use of a cost effective priority scheme to choose a flit that has to be moved to the side buffer. Experimental results shows that PBDeBAR reduces latency, deflection rate, buffer occupancy and link usage with respect to the existing minimally buffered deflection routers.

Network on Chip(NoC) is an efficient communication fabric for multi-core systems. As on-chip core count increases, area and power consumed by NoCs have to be considered seriously. Enhancing performance of NoCs under strict area and power budgets is of practical concern. In this paper, we propose CAERUS, a low-cost router that incorporates a novel arbitration policy that balances the opportunities to inject flits and an optimized ejection policy. Experimental results show that CAERUS reduces traversal latency of the flits in the network and sustain the throughput at higher injection rates as compared to existing low-cost router designs. The area and power expenditures are comparable to existing low cost router architectures.

The dramatic performance increase observed in the Internet over the last couple of years requires considerably enhanced router technology in order to provide the view of an efficient global network to applications and users. Improvements are needed with respect to data rate but also considering router functionality, for example, to support Quality of Service for multimedia applications. This paper gives a brief overview of some aspects related to router design in general and to route lookup in more detail. Several actual approaches to increase route lookup performance are introduced.

This paper gives the innovative idea of designing a router using multicrossbar switch in Network on Chip(NoC) . In Network-on-Chip architectures the input buffer can consume a large portion of the total power. Eliminating all input buffer would result in increased power consumption at high load, while reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar router design using elastic buffer by combining the advantage of both buffered and buffer less network. In the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router.&nbsp

This paper extends the System-on-Chip Wire (SoCWire) Network-On-Chip (NoC) with a reconfigurable router suitable for building FPGA-based NoC. Different configurations of the SoCWireRouter with a varying number of local and multi-dimensional ports have been used to create a number of equivalent networks. The system is prototyped in a FPGA-based PCIexpress board with the NoC connected to a softcore processor that acts as system master and monitor. The evaluation of equivalent networks for a fixed number of computing nodes under a synthetic and realistic traffic loads indicates the ideal SoCWireRouter topology depends on the design objectives and expected traffic pattern.