111 results on '"Rosmeulen, M."'
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2. A methodology for mechanical stress and wafer warpage minimization during 3D NAND fabrication
3. Gate Side Injection Operating Mode for 3D NAND Flash Memories
4. Pure-Metal Replacement Gate for Reliable 30 nm Pitch Scaled 3D NAND Flash
5. Gate MOSCAP Studies on Electroless Deposited Nickel Boron as Word Line Candidate Metal for Future Scaled 3-D NAND Flash
6. Modeling the Operation of Charge Trap Flash Memory–Part I: The Importance of Carrier Energy Relaxation
7. A Novel Ni-Al Alloy Metal Induced Lateral Crystallization Process for Improved Channel Conduction in 3-D NAND Flash
8. A Figure of Merit for Flash Memory Multi-Layer Tunnel Dielectrics
9. High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction
10. Liquid Memory and the Future of Data Storage
11. At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells
12. Understanding the kinetics of Metal Induced Lateral Crystallization process to enhance the poly-Si channel quality and current conduction in 3-D NAND memory
13. Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling
14. Program charge interference and mitigation in vertically scaled single and multiple-channel 3D NAND flash memory
15. A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics
16. Reliability of Mo as Word Line Metal in 3D NAND
17. Lateral Distribution of Electrons Trapped in Nitride Layers
18. Integration of Ruthenium-based Wordline in a 3-D NAND Memory Devices
19. Application of Single Pulse Dynamics to Model Program and Erase Cycling-Induced Defects in the Tunnel Oxide of Charge-Trapping Devices
20. Fabrication of MOS-integrated metallic single electron memories
21. Characterization of field-effect transistors with La2Hf2O7 and HfO2 gate dielectric layers deposited by molecular-beam epitaxy.
22. Characterization of field-effect transistors with La2Hf2O7 and HfO2 gate dielectric layers deposited by molecular-beam epitaxy
23. A platform for European CMOS image sensors for space applications
24. High speed TDI embedded CCD in CMOS sensor
25. HIGH SPEED TDI EMBEDDED CCD IN CMOS SENSOR.
26. Characterisation of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C-V
27. Stress and wafer warpage analysis of GaN thin film induced by transfer bonding process on 200mm Si substrate
28. Wafer bow of substrate transfer process for GaNLED on Si 8 inch
29. Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology
30. Analysis of LPCVD oxides for the passivation of high efficiency silicon solar cells
31. High speed TDI embedded CCD in CMOS sensor
32. Comparison of scaled floating body RAM architectures
33. Two-Pulse $C$–$V$ : A New Method for Characterizing Electron Traps in the Bulk of $ \hbox{SiO}_{2}/\hbox{high-}\kappa$ Dielectric Stacks
34. Electrical Characterization of Leaky Charge-Trapping High-$\kappa$ MOS Devices Using Pulsed $Q$– $V$
35. New Operating Mode Based on Electron/Hole Profile Matching in Nitride-Based Nonvolatile Memories
36. FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production
37. Nitride based FinFLASH memory device using multilevel Hot Carrier Program/Erase
38. Physical Understanding of SANOS Disturbs and VARIOT Engineered Barrier as a Solution
39. A Consistent Model for the SANOS Programming Operation
40. Ni-based FUSI gates: CMOS Integration for 45nm node and beyond
41. Exploration of the Circuit Potential of Multiple-Gate Field-Effect Transistors
42. Model for electron redistribution in silicon nitride
43. Reliability Prediction of Direct Tunneling RAM with SiON and HfSiON Tunnel Dielectrics Based on Transistor Leakage Current Measurements
44. Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs
45. An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies.
46. VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices
47. An easy-to-use mismatch model for the MOS transistor
48. Electrical Characterisation of Silicon-Rich-Oxide Based Memory Cells Using Pulsed Current-Voltage Techniques
49. Characterization of the VT-instability in SiO2/HfO2 gate dielectrics.
50. Quasi-Non Volatile Flatband-Voltage Shift in Metal-Oxide-Semiconductor Capacitors with Silicon-Rich-Oxide Dielectric
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