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CD measurements of advanced 3D-NAND Staircase process require development of new approaches in CD metrology [1]. The current CD SEM Contact Analysis used for 3D-NAND assumes that process control could be provided through a set of geometric parameters defining the contact shape (i.e. parameters of contact shape elliptic fit such as equivalent contact top diameter (Top CD), equivalent contact bottom diameter (Bottom CD), ellipticity, minor, major axis). The limitation of this approach for process control of complex structures was considered, and a new approach based on Grey Level Analysis of contact features in SEM images was proposed. However, this analysis is not enough for controlling the complicated 3D-NAND Staircase formation process steps, as contact holes with same geometric parameters but different depths cannot be separated by traditional CD SEM metrology measurement procedure (Figures 1 and 2). Thus, traditional CD SEM approach needs revisiting in order to work in situations where process control requires analysis of sophisticated Grey Level uniformity distribution. We propose a novel approach combining traditional metrology with machine learning methods. The essence of this new approach is to combine Grey Level attributes and traditional CD measured geometric parameters of the feature, obtained by traditional CD metrology flow, in a classification scheme (Figures 2 and 3). The proposed approach was qualified at Micron site demonstrating ~98% purity classification results. The proposed approach is generic and can be extended to a large variety of process control applications. Enhancing regular metrology flow with the capability to classify Etch process quality eliminates the need for the expensive and destructive cross-sectional SEM analysis. Furthermore, this method has a clear advantage during the early R&D phase of process development as it increases the usefulness of the in-line metrology tool while the process is still immature and unstable.

The growing demand for advanced DRAM technologies requires development of novel process control methodologies reflecting design rule shrinkage. The new challenges for CD SEM metrology of dense feature arrays of DRAM layers are widely considered in the literature and ITRS documents. In addition to traditional SEM metrology methods based on measurement of individual features, the development of novel measurement techniques is required for dense cell arrays at small nodes.[1-3] We considered a novel metrology of CDSEM Critical Dimension (CD) in dense arrays, formed as capacitors in advanced dynamic random-access memory (DRAM) layers. The proposed approach is based on traditional CDSEM metrology methodology with new developments providing flexibility, CD-style high precision, and large statistical sampling capabilities for advanced Statistical Process Control (SPC). The metrology challenge is solved through development of new algorithmic approaches for dense array measurements. The approach was validated on data simulation of extracting geometry (CD) parameters of actual DRAM cell structures and verified on real data.

Advanced FinFET device architecture generates new profile control requirement in 1× node and beyond. The corner at the intersection between the Gate and Fin is critical geometry for device yield and reliability. The residue-free corner at Gate-Fin interface after Polysilicon gate etch is desirable yet also a known challenge to detect and control. Current detection methods for gate poly footing, also known as gate skirt, are destructive with long turnaround time, resulting in slow progress in process development and high-volume process control. To meet the gap, e-Tilt imaging technique along with corner rounding algorithm has been developed on CDSEM platform to visualize and quantify residue at fin-gate intersection (poly-footing). In this paper, we'll discuss the challenges, approaches, and results associated with the first-in-industry implementation of the inline poly-footing detection within a HVM Fab. Two sets of DOEs (Design of Experiment) were conducted to validate the sensitivity to Etch recipes and Etch Chambers. The accuracy and precision of the poly-footing measurement were qualified with correlation to commonly used hammer test results and eTest results. Future study includes precision and throughput improvement to meet the need of 1× node.

Self-Aligned Quadruple Patterning (SAQP) is targeted to support the sub 10nm technology nodes. It is consisted of several process steps starting with lithography and Etch to define the pattern backbone. Followed by additional set of processes based on thin-films deposition and etch that quadruple the number of patterns, shrinking pattern and pitch sizes. Pattern roughness is derived from the physical and chemical characteristics of these process steps. It is changing with each of the SAQP process steps, based on material stack and the etch process characteristics. Relative to a sub 10 nm pattern sizes pattern, edge roughness can significantly impact pattern physical dimensions. Unless controlled it can increase the variability of device electrical performance, and reduce yield. In this paper we present the SAQP process steps and roughness characterization, performed with Power Spectral Density (PSD) methodology. Experimental results demonstrates the ability of PSD analysis to sensitively reflect detailed characterization of process roughness, guiding process development improvements, and enabling roughness monitoring for production.

At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R 2 being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R 2 being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.

In this paper we present a new methodology to calibrate and correct in line roughness measurements for Silicon Nano Wires (SiNW) fabrication processes. For successful implementation of these processes in industry, the Silicon Nano Wires (SiNW) with widths of 5–25 nm should be characterized in the framework of Secondary Electron Microscope(CD SEM) Metrology. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range[1]. Such small differences in roughness values provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5–25 nm and roughness of 0–1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and CD metrics.

In this paper we present physical characteristics of Silicon Nano Wires (SiNW) fabrication processes, in line SEM metrology measurements, and a new methodology to calibrate and correct in line roughness measurements, improving measurement accuracy. Silicon Nano Wires (SiNW) with widths of 5 - 25 nm were characterized. Hydrogen annealing was shown as a useful method for the fabrication of smooth suspended SiNW that are used to build gate-all-around MOSFETs [1]. Wires that were annealed in H2 exhibit surface roughness below 1 nm along the full length of the 100 nm long suspended wires. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range. Such small differences in roughness values, provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5 - 25 nm and roughness of 0 - 1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and metrics. Fabricated SiNW that received various smoothing and thinning treatments were measured with a CD-SEM. Results were compared to calibrate and validate the experimental CD-SEM results.

CD-SEMs fleet matching is a widely discussed subject and various approaches and procedures to determine it were described in the literature [1,2,4-6]. The different approaches for matching are all based on statistical treatment of CD measurements that are performed on dedicated test structures. The test structures are a limited finite set of features, thus the matching results should be treated as valid only for the specific defined set of test features. The credibility of the matching should be in question for different layers and specifically production layers. Since matching is crucial for reliable process monitoring by a fleet of CD-SEMs, the current matching approaches must be extended so that the matching will be only tool dependent and reproducible on all layers regardless their specific material or topographic characteristics. In our previous work [1] the new approach named "Physical Matching" was introduced and a new matching procedure based on the direct estimation of tool physical parameters was described. This approach extends the conventional matching methods to enable significant improvement of the matching between CD-SEM tools in production environment. In this work we present results of applying the physical matching method in FAB environment by using the physical parameters of the brightness and SNR, extend it to noise frequency domain characteristics monitoring, and enhanced collection uniformity. Improving the collection uniformity is also demonstrated and proved to be a significant factor. The advantage of the physical matching with noise spectra analysis approach for a case study is demonstrated. This method will enable detection of specific reasons for mismatching between the tools, based on analysis of specific frequencies that are resulted from known mechanical/electrical noise. The proposed procedure allows tool problems fixing before CD measurements are affected. In order to get a reliable visualization of the difference between two systems, new automatic and manual tool finger print methods were developed. The application of the proposed approach to vendor to vendor matching problem is considered.

CD-SEMs fleet matching is a widely discussed subject and various approaches and procedures to determine it were described in the literature. The different approaches for matching are all based on statistical treatment of regular CD measurements that are performed on dedicated test structures. The test structures are a limited finite set of features, thus the matching results should be treated as valid only for the specific defined set of test features. The credibility of the matching should be in question for different layers and specifically production layers. Since matching is crucial for reliable process monitoring by a fleet of CD-SEMs, the current matching approaches (such as TMU) must be extended so that the matching will be only tool dependent and reproducible on all layers regardless their specific material or topographic characteristics. In this work the term "Physical Matching" is introduced and a new matching procedure based on physical parameters is described. This approach extends the conventional matching methods to enable significant improvement of the matching between CD-SEM tools in production environment. To study and demonstrate the physical matching, we focus on the limited parameters set - the image brightness and Signal/Noise ratio(SNR). We test the sensitivity of CD measurements to changes in these parameters both on different test layers - Etch and Litho. We show that sensitivity of CD based measurements is low and reasonable change of the image brightness or SNR has small effect. The advantage of the physical matching approach for case study is demonstrated. The improved matching procedures are based on new targets that are used to measure the above image parameters directly. This way it is possible to characterize correctly the physical state of the measurement tool and guarantee the same image characteristics which in turn guarantee improved matching on all layers. In the framework of the proposed matching approach a proper determination of the minimal set of physical parameters that is needed to guarantee CD-SEM tools stability and matching should be included.

The importance of Critical Dimension (CD) roughness metrics such as Line and Contact edge roughness (LER, CER) and their associated width metrics (LWR, CWR) have been dealt with widely in the literature and are becoming semiconductor industry standards. With the downscaling of semiconductor fabrication technology, the accuracy of these metrics is of increasing importance. One important challenge is to separate the image noise (present in any SEM image) from the physically present roughness. An approach for the removal of the non-systematic image noise was proposed by J.Villarrubia and B.Bunday [Proc. SPIE 5752, 480 (2005)]. In the presented work this approach is tested and extended to deal with the challenge of noise removal in the presence of various types of systematic phenomena present in the imaging process such as CD variation. The study was carried out by means of simulated LWR and using real measurements.

The integration of embedded ferroelectric random access memory (FRAM) into a standard CMOS flow requires significant control and characterization of the patterned capacitor sidewall angle. The electrical functionality of the FRAM capacitor is highly dependent on the post-etch sidewall characteristics of the TiAlN hardmask and Ir/PZT/Ir capacitor film stack. In this study, we explored various options for determining the sidewall profile of these capacitors including scanning electron microscope (SEM), atomic force microscopy (AFM) and scatterometry. A series of capacitor samples with ranges of sidewall slopes from 60 degrees to 80 degrees was generated to test each measuring technique's robustness. All of the techniques demonstrated relatively accurate sidewall angle measurements of the high-angle capacitor profiles relative to cross-section SEMs. However, the CD SEM had difficulty identifying the top edge of the low-angle capacitor samples due to the large amount of profile roughness, which induced a large measurement error range. Additional optimization is required to improve the CD SEM's precision, before it would be a viable in-line monitor for the FRAM process. The AFM provided good accuracy and precision on the high-angle capacitor profiles, but the tip size limited the measurements to spaces larger than 120 nm. Furthermore, the AFM had a long move-acquire-measure (MAM) time of 5 minutes/site, which limited its throughput as an inline monitor. The scatterometer predicted bottom-stack sidewall angle measurements (2 trapezoid model) that were consistent with the cross-section SEMs, and it produced the lowest across wafer sidewall angle range. It also had the fastest MAM time of 5 seconds/site compared to the other techniques. However, it was difficult to generate an accurate scatterometry model due to the complex optical film stack that incorporated low surface reflectivity and higher surface roughness. While each technique had limitations, scatterometry appeared to be the most capable of inline sidewall angle monitoring.

The rapid shrink of device dimensions requires not only excellent 1D CD precision, but also characterization of corner rounding and line end shape. To meet this on-going trend the industry is in a quest for higher resolution metrology tools, which in-turn drives the use of SEM metrology as more crucial. The industry challenge is to reduce corner rounding and area loss. The metrology challenge, is to be able to measure accurately and precisely these characters, in order to be able to control your process. In our study we will introduce the development of a new algorithm for general shape analysis. The purpose of this algorithm is to allow effective control of the correspondence of the feature’s shape to the design geometry. The disadvantage of the standard CD SEM metric such as contact area was discussed widely in the literature but new metrics were not discussed yet. We consider the following issues and challenges related to the development of a generic algorithm for general shape 2D analysis. First stage of this algorithm is a generic segmentation of the two dimensional features. It should be robust to noise, as well as brightness and contrast changes. Output of this phase will be the contour representing the bottom of the feature. The second stage is the obtaining of new CD metrics for these contours, especially for contours corresponding to contacts with OPC structures. We consider the corner rounding as an example of such new metric. The same techniques can be elaborated for a large range of 2D structures with different levels of complexity. The obtaining of new metrics can be useful as handles for advanced process control (i.e. what to measure on the 2D feature with complex shape such as contact with OPC structures). We consider in this paper the application of the developed metrics for reticle contact with OPC structure monitoring problem that simulates a high level of complexity.

Downscaling of semiconductor fabrication technology nodes brought forth a need to reassess the accuracy of 3D metrology. Accuracy is defined relative to a reference tool measurement. The authors have studied the accuracy of 3D SEM measurement results for various feature geometries and materials, matching the results to Monte Carlo simulations. Analysis of the SEM images based on an analytical model was performed. Careful analysis of the matching curves for 3D algorithm results and reference data (geometric parameters of the feature) reviled an appropriate behavior of algorithm in the vicinity of the nominal process window, and for sufficiently small feature rounding (production node). We performed matching of 3D CD SEM measurement to reference geometry data using Monte Carlo simulation. We analyzed the accuracy of measurement for a wide range of the feature geometry parameters (height, sidewall angle, top and bottom rounding). The simple physical model for corner rounding estimation is considered. We perform the model waveform analysis of the feature rounding influence on the height measurements. Serving as a process-monitoring tool, the algorithm performance was found in agreement with the required tolerance typical of the nominal process window ± 10%. Serving on extreme R&D, where rounding further away from the nominal window ± 10% is counted significant, there lie observable deviations in accuracy of height and sidewall angle measurement. These are explained through extreme corner rounding effects.

The rapid shrink of device dimensions requires reduced feature size on reticles and hence, improved CD uniformity and CD measurement precision in order to achieve tight process control. To meet this on-going trend the industry is in a quest for higher resolution metrology tools, which in-turn drives the use of SEM metrology into standard mask and manufacturing process. This paper concentrates on one specific area of Mask Metrology, being measurement of 2D (Two Dimensional) features such as contacts with sub resolution features -0 using a new SEM metrology tool, the Applied Materials' RETicleSEM. We consider the basic requirements for performing 2D measurements on a reticle as well as the algorithmic development to generalize a solution for these requirements. We consider three main requirements from such algorithm: a) It should be generic and deal with general shape features; b) It should provide new geometric metrics - such as contact area and corner roundness; c) It should measure new geometric patterns such as OPC (Optical Proximity Corrections) features and small CDs. We discuss the following issues/challenges related to the development of a generic algorithm for general shape 2D analysis: a) Limitations of the standard approach for Contacts qualification based on the Area loss measurement (Area based). b) A generic segmentation of the feature. It should be robust to noise, as well as brightness and contrast changes. c) The complexity of two dimensional general shape features metrology, especially OPC measurements. Limitations of the standard CD SEM metrology based on metrics describing simple geometric shapes such as ellipses and lines. The obtaining of new metrics can be useful as handles for advanced process control (i.e. what to measure on the 2D feature with complex shape such as contact with OPC structures).

Downscaling of semiconductor fabrication technology nodes brought forth a need to reassess the accuracy of 3D metrology. Accuracy is defined relative to a reference tool measurement. The authors have studied the accuracy of 3D SEM measurement results for various feature geometries and materials, matching the results to Monte Carlo simulations. Analysis of the SEM images based on an analytical model was performed. Accuracy of 3D algorithm for nominal process window monitoring is shown.

SEM Metrology becomes the standard metrology for the mask industry, as the precision and accuracy requirements tighten continuously. At the same time, analysis of general shape features becomes an important task in wafer metrology. In this paper we consider the basic requirements and suggested implementations for performing 2D metrology on reticles and wafers, [i.e. measurements of OPC (Optical Proximity Correction) structures, End of Lines, Dual Damascene and Corner Rounding]. The authors consider the following challenges related to the development of a generic algorithm for general shape 2D analysis: (1) A generic segmentation of the feature. It should be robust to noise, as well as brightness and contrast changes. (2) The complexity of two dimensional general shape features metrology. Standard CD SEM metrology is based on metrics describing simple geometric shapes such as ellipses and lines). (3) Obtaining such metrics that can be used as handles for process control (i.e. what to measure on the 2D feature). In the first part of the paper we describe a novel algorithm for segmentation and geometric analysis of general shape features based on a Smoothing Spline and the methods of differential geometry. Next, we consider the numerical methods implemented for shape analysis of noisy contours. In the second part of the paper the performance of our methods on synthetic contours of circular arc with different noise levels is demonstrated. We conclude with sample results of several suggested metrics measured on real SEM images of reticles and wafers.

SEM Metrology becomes the standard metrology for the mask industry, as the precision and accuracy requirements tighten continuously. In this paper we consider the basic requirements for performing 2D measurements of the reticle, such as contact area and corner roundness as well as the algorithmic development to generalize a solution for these requirements. We consider three main requirements from such algorithm: a) To be generic and deal with general shape features. b) To measure new geometric metrics - such as contact area and corner roundness. c) TO measure new geometric patterns suhc as OPC features and small CDs. These challenges require the development of new algorithms for CD metrology. These algorithsm perform detection and measurement of new geoemtric objects, and provide the repeatability and robustness for reticle production process control. In the first part of the paper we will describe the novel algorithm for detection of general shape features - "Region Connectivity Extraction". In the second part of the paper, we will provide mathematical tools that we have implemented for analyzis of corner roundness of noisy contours and demonstrate the performance of these algorithms for synthetic contours of different shapes with different noise levels. We will conclude with the application of our algorithm and analysis of real SEM images of the reticle features.

At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R2 equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.