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Silicon specimens containing p-n junctions have been prepared for examination by off-axis electron holography using focused ion beam (FIB) milling. FIB milling modifies the surfaces of the specimens due to gallium implantation and the creation of defects which has the effect of reducing the active dopant concentration measured during electrical characterization. Here we show that although this damage can be removed by using low temperature annealing, the presence of surface charge will modify the electrical potentials in the specimens and limit the dopant concentration that can be measured. [ABSTRACT FROM AUTHOR]

Silicon specimens containing p-n junctions are prepared and examined by off-axis electron holography using focused ion beam (FIB) milling. The studies have shown that the presence of surface charge might modify the electrical potentials in the specimens and has limited the dopant concentration that can be measured.

An atomistic model to account for the impact of stress during solid phase epitaxial regrowth (SPER) is proposed. This model is based on the lattice kinetic Monte Carlo method. It has been compared with experimental data of regrowth velocity as a function of hydrostatic and non-hydrostatic stresses. In particular, it permits to provide a physical explanation of the observations upon in-plane uniaxial stress based on the assumption that {100} events occur through a dual-timescale atomistic mechanism. Our model also catches the fact that compressive normal uniaxial stress and hydrostatic pressure result in an enhancement of the regrowth velocity with a similar activation volume. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices. [ABSTRACT FROM AUTHOR]

We demonstrate that state-of-the-art off-axis electron holography can be used to map active dopants in silicon nanowires as thin as 60 nm with 10 nm spatial resolution. Experiment and simulation demonstrate that doping concentrations of 10(19) and 10(20) cm(-3) can be measured with a detection threshold of 10(18) cm(-3) with respect to intrinsic silicon. Comparison of experimental data and simulations allows an estimation of the charge density at the wire-oxide interface of -1 x 10(12) electron charges cm(-2). Off-axis electron holography thus offers unique capabilities for a detailed analysis of active dopant concentrations in nanostructures.