4,881 results on '"Ring Oscillator"'
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2. [formula omitted] Parallel paths for non-linearity mitigation in ring oscillator based analog-to-digital conversion
- Author
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Gutierrez, Eric, Alvero-Gonzalez, Leidy Mabel, and Garvi, Ruben
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- 2023
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3. A Study of the Optimal Logic Combinations of RO-Based PUFs on FPGAs to Maximize Identifiability.
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Aparicio-Téllez, Raúl, Garcia-Bosque, Miguel, Díez-Señorans, Guillermo, Aznar, Francisco, and Celma, Santiago
- Abstract
One of the challenges that wireless sensor networks (WSNs) need to address is achieving security and privacy while keeping low power consumption at sensor nodes. Physically unclonable functions (PUFs) offer a challenge–response functionality that leverages the inherent variations in the manufacturing process of a device, making them an optimal solution for sensor node authentication in WSNs. Thus, identifiability is the fundamental property of any PUF. Consequently, it is necessary to design structures that optimize the PUF in terms of identifiability. This work studies different architectures of oscillators to analyze which ones exhibit the best properties to construct a RO-based PUF. For this purpose, Generalized Galois Ring Oscillators (GenGAROs) are used. A GenGARO is a novel type of oscillator formed by a combination of up to two input logical operations connected in cascade, where one input is the output of the previous operation and the other is the feedback signal. GenGAROs include some previously proposed oscillators as well as many new oscillator designs. Thus, the architecture of GenGAROs is analyzed to implement a GenGARO-PUF on an Artix-FPGA. With this purpose, an exhaustive study of logical operation combinations that optimize PUF performance in terms of identifiability has been conducted. From this, it has been observed that certain logic gates in specific positions within the oscillator contribute to constructing a PUF with good properties, and by applying certain constraints, any oscillator generated with these constraints can be used to construct a PUF with an equal error rate on the order of or below 10 − 11 using 100-bit responses. As a result, a design methodology for FPGA-based RO-PUFs has been developed, enabling the generation of multiple PUF primitives with high identifiability that other designers could exploit to implement RO-based PUFs with good properties. [ABSTRACT FROM AUTHOR] more...
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- 2024
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4. Key Role of Cold-Start Circuits in Low-Power Energy Harvesting Systems: A Research Review.
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Shi, Xiao, Cai, Mengye, and Jiang, Yanfeng
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ENERGY harvesting ,ENERGY storage ,TECHNOLOGICAL innovations ,POWER resources ,ARTIFICIAL intelligence - Abstract
The primary functions of an energy harvesting system include the harvesting, transformation, management, and storage of energy. Until now, various types of energy, with different power levels, have been harvested and stored by the energy harvesting system. In low-power scenarios, such as microwaves, sound, friction, and pressure, a specific low-power energy harvesting system is required. Due to the absence of an external power supply in such systems, cold-start circuits play a crucial role in igniting the low-power energy harvesting system, ensuring a reliable start-up from the initial state. This paper reviews the categorization and characteristics of energy harvesting systems, with a focus on the design and performance parameters of cold-start circuits. A tabular comparison of existing cold-start strategies is presented herein. The study demonstrates that resonance-based integrated cold-start methods offer significant advantages in terms of conversion efficiency and dynamic range, while ring oscillator-based integrated cold-start methods achieve the lowest start-up voltage. Additionally, the paper discusses the challenges of self-starting and future research directions, highlighting the potential role of emerging technologies, such as artificial intelligence (AI) and neural networks, in optimizing the design of energy harvesting systems. [ABSTRACT FROM AUTHOR] more...
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- 2024
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5. TCAD Design of a 3-Terminal Inverter Using Non-Align Double Gates and Its Performance Assessment.
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Sri Lakshmi Sangam and Arun Kumar Sinha
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HAFNIUM oxide , *FIELD-effect transistors , *FREQUENCIES of oscillating systems , *SILICA , *SILICON oxide - Abstract
This work presents the design and simulation analysis of a compact nano-scale single-device inverter structure of 220 nm length and an oscillator by using non-aligned double gate MOS technology. The proposed non-aligned double gate inverter (NADGI) structure is a three-terminal device compared to the conventional four-terminal double gate field effect transistor. The performance of the NADGI was tested using two gate oxide materials: silicon dioxide (SiO2, k = 3.9) and hafnium dioxide (HfO2, k = 24), showing improved results in terms of delay, power consumption, and energy efficiency, especially with low-k materials. The voltage-gains of NADGI with low-k, and high-k materials are, –14 and –21 V/V, respectively. NADGI with low-k materials results in lower values for noise margin high (0.47 V), and noise margin low (0.397 V). By using the graphical method, the optimal supply voltage of the NADGI was determined and is nearly 0.65 V. At optimal supply voltage with 1 GHz signal, and CL = 10 fF, the NADGI with low-k gate oxide gives tp = 6.2 ps, EDP = 0.25 fJ-ps, PDP = 44.6 aJ, high-k gate oxide gives tp = 7 ps, EDP = 0.44 fJ-ps, PDP = 64.46 aJ. Simulation results indicate that NADGI with low-k materials performs better at high frequencies and lower power consumption, while high-k materials are more suitable for driving large capacitors. Additionally, a 5-stage ring oscillator was tested at a supply voltage of 0.65 V. Under a load capacitance of 1 fF, the NADGI oscillator with low-k, and high-k gives an oscillation frequency of 25 and 16.6 GHz respectively. The simulation results show that NADGI with low-k gate oxide achieves higher oscillation frequencies compared to high-k materials. [ABSTRACT FROM AUTHOR] more...
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- 2024
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6. High-Confidence Remote Power Analysis on Heterogeneous SoCs
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Fellah-Touta, Anis, Bossuet, Lilian, and Lara-Nino, Carlos Andres
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- 2024
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7. Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors.
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Jeong, Jinsu, Lee, Sanguk, and Baek, Rock-Hyun
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FIELD-effect transistors , *TRANSISTORS , *FREQUENCIES of oscillating systems , *SILICON , *LOW temperatures - Abstract
The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs. [ABSTRACT FROM AUTHOR] more...
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- 2024
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8. Performance Evaluation of Nano-scale Core–Shell Junctionless FETs in the Designing of Ultralow-Power Inverter and Ring Oscillator.
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Seifollahi, Samaneh, Ziabari, Seyed Ali Sedigh, and kiani-Sarkaleh, Azadeh
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FIELD-effect transistors ,THRESHOLD voltage - Abstract
A core–shell junctionless field-effect transistor (CS-JLFET) has been utilized for designing ultra-low-power inverter and ring oscillator circuits. The core doping can be considered as similarly doped or oppositely doped (OD) shells. The presence of the core with the opposite impurity of the shells in the OD-CS-JLFET leads to depleting the volume, and, as a result, obtaining the optimal off-current ( I off ) and the ON-to-OFF current ratio ( I on / I off ). Achieving an acceptable off-current in the OD-CS-JLFET helped to improve the power consumption of the inverter and ring oscillator circuits. In addition, the CS technique can be regarded as a beneficial approach to adjust the threshold voltage. The simulation results reveal that the power consumption of the inverter based on OD-CS-JLFET is improved by 55% compared to a JLFET. Also, with the design of the three-stage ring oscillator based on the OD-CS-JLFET, the power consumption obtained acceptable values of 99.15 μ W . [ABSTRACT FROM AUTHOR] more...
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- 2024
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9. An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage.
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Diaz-Fortuny, Javier, Saraza-Canflanca, Pablo, Bury, Erik, Degraeve, Robin, and Kaczer, Ben
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INTEGRATED circuits ,HOT carriers ,AUTOMOTIVE electronics ,INTEGRATED circuits manufacturing ,ELECTRONIC systems ,ACCELERATED life testing - Abstract
The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC. [ABSTRACT FROM AUTHOR] more...
- Published
- 2024
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10. Spice Simulation of Solution Processed Bottom Gate Bottom Contact Organic Thin Film Transistor
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Puttur, Saiganesh, Imroze, Fiheon, Aniruddhan, Sankaran, Dutta, Soumya, Singh, Rajendra, editor, Singh, Madhusudan, editor, and Kapoor, Ashok, editor
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- 2024
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11. Programmable RO (PRO): A Multipurpose Countermeasure Against Side-Channel and Fault Injection Attack
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Yao, Yuan, Kiaei, Pantea, Singh, Richa, Tajik, Shahin, Schaumont, Patrick, Szefer, Jakub, editor, and Tessier, Russell, editor
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- 2024
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12. Carry-Chain Based Ring Oscillator for FPGA: Design and Characterization
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Spagnolo, Fanny, Corsonello, Pasquale, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Tan, Kay Chen, Series Editor, Ciofi, Carmine, editor, and Limiti, Ernesto, editor more...
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- 2024
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13. FPGA-Based True Random Number Generator Architecture Using 15-Bit LFSR and ADPLL
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Meitei, Huirem Bharat, Kumar, Manoj, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Tan, Kay Chen, Series Editor, Swain, Bibhu Prasad, editor, and Dixit, Uday Shanker, editor more...
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- 2024
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14. Design and Study the Performance of a CMOS-Based Ring Oscillator Architecture for 5G Mobile Communication
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Abdul Rahman, Siddharth Kishore, and A. R. Abdul Rajak
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vlsi ,5g ,cmos ,ring oscillator ,vco ,mobile communication. ,Technology (General) ,T1-995 ,Social sciences (General) ,H1-99 - Abstract
Oscillator circuits are used to make accurate and reliable clock signals for systems as simple as a wristwatch and as complicated as satellites, which are important for long-distance communication. There are many ways to build an oscillator circuit, using either passive or active parts. Each option has pros and cons, but at the current level of mobile communication development, the most important things are interoperability and low power use. This need has driven the development of compact, battery-operated electronics, and Very Large-Scale Integration (VLSI)-based ring oscillators provide the ideal solution. These oscillators ought to dissipate less power, have a large tuning range, and be compact. The paper presents a novel Complementary Metal Oxide Silicon (CMOS) ring oscillator that serves as a Voltage Controlled Oscillator. The suggested architecture utilizes the advantages of both a current-starved ring oscillator and a negative-skewed delay by combining their constituent parts. The proposed architecture has a control voltage of 1.15 V and a supply voltage of 2 V, generating a 9.35 GHz dominant frequency with a 13.82% harmonic distortion between the inputs and outputs. The proposed architecture can implement 5G-based applications that require high frequency and low power by carefully selecting the passive components within the design. Doi: 10.28991/ESJ-2024-08-01-020 Full Text: PDF more...
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- 2024
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15. Key Role of Cold-Start Circuits in Low-Power Energy Harvesting Systems: A Research Review
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Xiao Shi, Mengye Cai, and Yanfeng Jiang
- Subjects
low-power energy harvesting system ,cold-start circuit ,LC resonant ,ring oscillator ,Applications of electric power ,TK4001-4102 - Abstract
The primary functions of an energy harvesting system include the harvesting, transformation, management, and storage of energy. Until now, various types of energy, with different power levels, have been harvested and stored by the energy harvesting system. In low-power scenarios, such as microwaves, sound, friction, and pressure, a specific low-power energy harvesting system is required. Due to the absence of an external power supply in such systems, cold-start circuits play a crucial role in igniting the low-power energy harvesting system, ensuring a reliable start-up from the initial state. This paper reviews the categorization and characteristics of energy harvesting systems, with a focus on the design and performance parameters of cold-start circuits. A tabular comparison of existing cold-start strategies is presented herein. The study demonstrates that resonance-based integrated cold-start methods offer significant advantages in terms of conversion efficiency and dynamic range, while ring oscillator-based integrated cold-start methods achieve the lowest start-up voltage. Additionally, the paper discusses the challenges of self-starting and future research directions, highlighting the potential role of emerging technologies, such as artificial intelligence (AI) and neural networks, in optimizing the design of energy harvesting systems. more...
- Published
- 2024
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16. Ultra Low Power and High Speed Electronic Circuits Using Double Gate Tunnel Field Effect Transistor
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Kumar, Ch. Pavan and Sivani, K.
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- 2024
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17. Improving the accuracy for amplitude and frequency of analytical equation of single-ended ring oscillators based on circuit and transistor parameters
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Moradnezhad, Mehrdad and Miar Naimi, Hossein
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- 2023
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18. Bias dependence in statistical random telegraph noise analysis based on nanoscale CMOS ring oscillators.
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Ramazanoglu, Semih, Michalowska-Forsyth, Alicja, and Deutschmann, Bernd
- Abstract
Copyright of e & i Elektrotechnik und Informationstechnik is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) more...
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- 2024
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19. A True Random Number Generator Based on Race Hazard and Jitter of Braided and Cross-Coupled Logic Gates Using FPGA
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Hossam O. Ahmed, Donghoon Kim, and William J. Buchanan
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True random number generator (TRNG) ,race hazard ,ring oscillator ,field programmable gate array (FPGA) ,jitter ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
In the contemporary digital landscape, security has become a vital element of our existence. The growing volume of sensitive information being stored and transmitted over networks necessitates the implementation of robust security measures. Cryptographic algorithms, which are critical for protecting user data privacy, rely on cryptographic keys to ensure data security. True Random Number Generators (TRNGs) are essential to numerous vital security applications. In this paper, we propose a novel Braided and Hybrid Cross-Coupled Entropy Source (B+HCCES) TRNG module. The proposed B+HCCES TRNG module generates random numbers based on the race hazard and jitter of braided and cross-coupled combinational logic gates. The B+HCCES architecture has been designed using VHDL, and the targeted Field-Programmable Gate Array (FPGA) is the Intel Cyclone V 5CGXFC9D6F27C7 chip. The B+HCCES module operates at a fixed sampling frequency of 300 MHz, generated by an embedded phase-locked loop. The B+HCCES module demonstrates an enhanced throughput of 3.33 times compared to the state-of-the-art, while still maintaining a comparably lightweight architecture. The experimental results demonstrate that the generated random sequence successfully passes the NIST SP800-90B and BSI AIS-31 tests. more...
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- 2024
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20. Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications
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Vakkalakula Bharath Sreenivasulu, Aruna Kumari Neelam, Asisa Kumar Panigrahy, Lokesh Vakkalakula, Jawar Singh, and Shiv Govind Singh
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CMRR ,CMOS inverter ,IRDS ,GAAFET ,operational transconductance amplifier (OTA) ,ring oscillator ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
In this study, for the very first time developing of n- and p-type 3-D single-channel (SC) FinFET and gate-all-around (GAA) Multi-Bridge-Channel FETs (MBCFET) like nanowire FET (NWFET) and nanosheet FET (NSFET) are benchmarked towards device and circuit levels which are emulated with International Road map for Devices and Systems (IRDS) for sub-5-nm technology nodes. Compared to the FinFET, the MBCFETs exhibits higher ON-current ( $I_{\mathrm {ON}})$ , switching ratio ( $I_{\mathrm {ON}}/I_{\mathrm {OFF}})$ , lower subthreshold-swing (SS) and drain-induced barrier lowering (DIBL). Except for extended parasitic capacitances ( $C_{\mathrm {para}})$ , our benchmarking results show that the NWFET and NSFET achieve the high-performance (HP) and low-power (LP) goals of IRDS. Furthermore, the NSFET delivers superior performance towards DC and analog/RF metrics. The cut-off frequency ( $f_{\mathrm {T}})$ and gain bandwidth product (GBW) are higher (because of high $I_{\mathrm {ON}})$ in the case of NSFET, even though the capacitive effect is significant. Further, the logic circuit applications like CMOS inverter and ring oscillator (RO) circuits are analyzed and compared in detail. The CMOS inverters propagation delays ( $\tau _{\mathrm {p}})$ is reduced to 31% from FinFET to NWFET and 12% from NWFET to NSFETs is noticed. Also, the NWFET and NSFET based ROs offer 39% and 56% high oscillation frequency ( $f_{\mathrm {osc}})$ compared to that of FinFET counterpart. Finally, the single stage current mirror performance and operational transconductance amplifiers (OTA) gain and common mode rejection ratio (CMRR) are carried out towards analog and mixed-mode circuit applications. more...
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- 2024
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21. Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective
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Neelam Aruna Kumari, V. Bharath Sreenivasulu, Vikas Vijayvargiya, Abhishek Kumar Upadhyay, J. Ajayan, and M. Uma
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CombFET ,TreeFET ,NSFET ,temperature ,CMOS inverter ,ring oscillator ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
In this article, the comparison of nanosheet (NS) FET, CombFET, and TreeFETs at advanced technology nodes is performed. Initially, the DC metrics like $I_{\mathrm {ON}}$ , $I_{\mathrm {ON}}/I_{\mathrm {OFF}}$ and $I_{\mathrm {D}} - V_{\mathrm {DS}}$ are dominated by TreeFET compared to Comb and NSFET. The TreeFET exhibits higher $I_{\mathrm {ON}}$ and ensures high-performance (HP) applications at advanced nodes. However, the NSFET continues as a better performer towards low power (LP) applications. The TreeFET dominates the performance and switching performance for temperature variation. At lower temperatures, the NS, Comb, and TreeFETs have a marginal impact on $I_{\mathrm {OFF}}$ . The analog performance is dominated by TreeFET due to higher $I_{\mathrm {ON}}$ . The NSFET exhibits lower $C$ gd and $C$ gs due to the absence of interbridges (IB) between channels. The RF performance is also dominated by Comb and TreeFETs due to the presence of IBs. Further, TreeFET based CMOS inverter outperforms in terms of switching current ( $I_{\mathrm {SC}}$ ) compared to the NSFET and CombFET counterparts. The 27-stage ring oscillator (RO) performance of TreeFET dominates Comb and NSFET with 11.56 GHz ensuring driving radio frequency applications. Thus, the paper will give deep insights into the performance of emerging FETs at both device as well as circuit levels. more...
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- 2024
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22. Recent Start-Up Techniques Intended for TEG Energy Harvesting: A Review
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Mahmoud Ahmed, Sebastien Genevey, Mohamed Ali, Yvon Savaria, and Yves Audet
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TEG ,EH ,start-up techniques ,ring oscillator ,Schmitt Trigger ,IoT ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
The growing number of energy-autonomous applications raises the need for reliable DC energy harvesting techniques such as Thermoelectric Generators (TEGs). One key issue, however, is the minimum voltage (40–60 mV) required for start-up in small TEG energy harvesting sources. We review in this paper recent start-up solutions for TEG energy harvesting technologies. Different solutions have been categorized into 5 main approaches: external battery, extra-fabrication-process-based, transformers, multisource energy harvesting, and DC-AC-DC conversion using oscillators. The “DC-AC-DC conversion ring oscillators” approach is then shown to be the most promising solution in line with DC energy harvesting applications because it offers several advantages over other approaches, such as allowing full integration with good performance, compatibility with regular CMOS technology, and lower cost. Then, its different implementations are discussed and a detailed analysis is provided to identify their respective advantages and limitations. more...
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- 2024
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23. A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-Up Circuits in DC Energy Harvesting Systems
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Mahmoud Ahmed, Aref Trigui, Sebastien Genevey, Yves Audet, and Yvon Savaria
- Subjects
TEG ,start-up techniques ,ring oscillator ,Schmitt trigger ,cold start-up ,dynamic body biasing ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
Implementing fully integrated start-up energy harvesting (EH) systems is very challenging. The most popular start-up circuit implementations use a low-voltage ring oscillator (RO). The characteristics of this RO rapidly deteriorate at VDD values below the transistor’s threshold voltage. A novel delay cell based on a Schmitt trigger (ST) inverter leveraging dynamic body biasing (DBB) is proposed to mitigate this deterioration. The RO of the proposed cell, implemented in a 22 nm FD-SOI CMOS technology, is compared against conventional and state-of-the-art circuits implemented in the same technology. Simulated results show the proposed RO achieves the highest output swing and DC gain within the 40 to 100 mV supply voltage range. A prototype chip comprising a 27-stage RO was fabricated and tested in a 22 nm FD-SOI CMOS technology. When fed by a 50 mV supply voltage, this RO produces an output swing of $\mathbf {80\%}$ of that voltage while oscillating at a 0.8 kHz clock frequency and consuming 300 pW. In reported experiments, oscillations started with VDD as low as 32 mV. To the authors’ knowledge, the proposed CMOS RO operates with the second-lowest ever reported supply voltage. Combining its low power and low area, this RO is most suitable for EH systems with restricted power and area budget. more...
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- 2024
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24. Calibration of Ring Oscillator-Based Integrated Temperature Sensors for Power Management Systems.
- Author
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El-Zarif, Nader, Amer, Mostafa, Ali, Mohamed, Hassan, Ahmad, Oukaira, Aziz, Fayomi, Christian Jesus B., and Savaria, Yvon
- Subjects
- *
TEMPERATURE sensors , *CALIBRATION , *DC-to-DC converters , *TEMPERATURE measurements , *SYSTEMS on a chip , *QUADRATIC programming - Abstract
This paper details the development and validation of a temperature sensing methodology using an un-trimmed oscillator-based integrated sensor implemented in the 0.18- μ m SOI XFAB process, with a focus on thermal monitoring in system-on-chip (SoC) based DC-DC converters. Our study identifies a quadratic relationship between the oscillator output frequency and temperature, which forms the basis of our proposed calibration mechanism. This mechanism aims at mitigating process variation effects, enabling accurate temperature-to-frequency mapping. Our research proposes and characterizes several trimming-free calibration techniques, covering a spectrum from zero to thirty-one frequency-temperature measurement points. Notably, the Corrected One-Point calibration method, requiring only a single ambient temperature measurement, emerges as a practical solution that removes the need for a temperature chamber. This method, after adjustment, successfully reduces the maximum error to within ± 2.95 °C. Additionally, the Two-Point calibration method demonstrates improved precision with a maximum positive error of +1.56 °C at −15 °C and a maximum negative error of −3.13 °C at +10 °C ( R 2 value of 0.9958). The Three-Point calibration method performed similarly, yielding an R 2 value of 0.9956. The findings of this study indicate that competitive results in temperature sensor calibration can be achieved without circuit trimming, offering a viable alternative or a complementary approach to traditional trimming techniques. [ABSTRACT FROM AUTHOR] more...
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- 2024
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25. Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA.
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Sobas, Justin and Marc, François
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INTEGRATED circuits ,TRANSISTORS ,METAL oxide semiconductor field-effect transistors - Abstract
Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions ( V n o m ≤ V s t r e s s ≤ 1.3 V n o m and 25 ° C ≤ T s t r e s s ≤ 115 ° C ) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50 % and 70 % of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1 % , which is a first indicator proving the FPGAs' good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA. [ABSTRACT FROM AUTHOR] more...
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- 2024
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26. Discontinuity-Induced Bifurcations and Chaos in a Linear Ring Oscillator with a Piecewise Linear Reverse Coupling.
- Author
-
Horikawa, Yo
- Subjects
- *
HARMONIC oscillators , *OPERATIONAL amplifiers , *DISCONTINUOUS functions , *HOPF bifurcations , *ANALOG circuits , *NONLINEAR oscillators , *ATTRACTORS (Mathematics) - Abstract
The bifurcations of periodic solutions and the generation of chaos in a ring of three unidirectionally coupled linear elements with a single reverse coupling through a piecewise linear function are considered. A discontinuous and a continuous piecewise linear function are employed for the reverse coupling. A chaotic attractor is generated immediately through a Hopf-like boundary equilibrium bifurcation of a focus in both cases. A chaotic attractor is also generated directly through a grazing bifurcation in the case of the discontinuous function, which is replaced with a cascade of period-doubling bifurcations in the case of the continuous function. A chaotic oscillation with the same form is also observed in an experiment on an analog circuit constructed with operational amplifiers. In a smooth version of the system, a ring of three unidirectionally coupled sigmoid neurons with a reverse coupling, the Hopf-like boundary equilibrium bifurcation is replaced with a period-doubling cascade following after the Hopf bifurcation. [ABSTRACT FROM AUTHOR] more...
- Published
- 2023
- Full Text
- View/download PDF
27. Study and Performance Comparison of Coupled Ring Oscillator
- Author
-
Pendyala, Shirisha, Ziauddin Jahangir, Mohd., Chandra Sekhar, Paidimarry, Chan, Albert P. C., Series Editor, Hong, Wei-Chiang, Series Editor, Mellal, Mohamed Arezki, Series Editor, Narayanan, Ramadas, Series Editor, Nguyen, Quang Ngoc, Series Editor, Ong, Hwai Chyuan, Series Editor, Sachsenmeier, Peter, Series Editor, Sun, Zaicheng, Series Editor, Ullah, Sharif, Series Editor, Wu, Junwei, Series Editor, Zhang, Wei, Series Editor, Raj, Bhiksha, editor, Gill, Steve, editor, Calderon, Carlos A.Gonzalez, editor, Cihan, Onur, editor, Tukkaraja, Purushotham, editor, Venkatesh, Sriram, editor, M. S., Venkataramayya, editor, Mudigonda, Malini, editor, Gaddam, Mallesham, editor, and Dasari, Rama Krishna, editor more...
- Published
- 2023
- Full Text
- View/download PDF
28. Unified Physical Parameters-Based Analytical Drain Current Model of Amorphous-InGaZnO TFTs for Emerging Display Technology
- Author
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Sharma, Ashima, Bahubalindruni, Pydi Ganga, Bharti, Manisha, Barquinha, Pedro, Kacprzyk, Janusz, Series Editor, Gomide, Fernando, Advisory Editor, Kaynak, Okyay, Advisory Editor, Liu, Derong, Advisory Editor, Pedrycz, Witold, Advisory Editor, Polycarpou, Marios M., Advisory Editor, Rudas, Imre J., Advisory Editor, Wang, Jun, Advisory Editor, Marriwala, Nikhil, editor, Tripathi, C.C., editor, Jain, Shruti, editor, and Kumar, Dinesh, editor more...
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- 2023
- Full Text
- View/download PDF
29. True Random Number Generators
- Author
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Tehranipoor, Mark, Pundir, Nitin, Vashistha, Nidish, Farahmandi, Farimah, Tehranipoor, Mark, Pundir, Nitin, Vashistha, Nidish, and Farahmandi, Farimah
- Published
- 2023
- Full Text
- View/download PDF
30. Tamper Detection
- Author
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Tehranipoor, Mark, Pundir, Nitin, Vashistha, Nidish, Farahmandi, Farimah, Tehranipoor, Mark, Pundir, Nitin, Vashistha, Nidish, and Farahmandi, Farimah
- Published
- 2023
- Full Text
- View/download PDF
31. Automatic Balancing of 'Arbiter' Physical Unclonable Function Paths
- Author
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A. Yu. Shamyna and A. A. Ivaniuk
- Subjects
physical cryptography ,“arbiter” physical unclonable functions ,ring oscillator ,automatic balancing ,programmable logic integrated circuits ,Electronics ,TK7800-8360 - Abstract
The features of building on the basis of programmable logic integrated circuits of “arbiter” physical unclonable functions (APUF) are considered. The problem of asymmetry of pairs of APUF paths is indicated and the negative impact of this phenomenon on their characteristics is noted. A time measuring system based on a ring oscillator scheme, which is used to analyze the time characteristics of APUF paths, is described. A method for automatic balancing of signal propagation delays through the APUF paths based on the calculation of the corrective value is proposed. The consistency of the proposed balancing technique is experimentally confirmed based on the improvement in the characteristics of the APUF after its implementation. A digital scheme of this technique is presented, which can form the basis for the development of a delay auto correction scheme through APUF paths with different levels of autonomy. more...
- Published
- 2023
- Full Text
- View/download PDF
32. A Comprehensive Analysis of Nanosheet FET and its CMOS Circuit Applications at Elevated Temperatures.
- Author
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Kumari, N. Aruna and Prithvi, P.
- Abstract
The Nanosheet Field Effect Transistor (NSFET) has been shown to be a viable candidate for sub-7-nm technology nodes. This paper assesses and compares the NSFET performance at elevated temperatures ranging from 25
0 to 2000 C at both device and circuit levels. As the temperature increases from 250 to 2000 C, the electron mobility is reduced by 68% due to the severe scattering mechanism. It is observed that the electrical performance degraded with rise in temperature. Moreover, the temperature variations on analog/RF FOMs like gm , intrinsic gain (Av0 ), cut-off frequency (fT ), intrinsic delay (τ ), transconductance frequency product (TFP), gain bandwidth product (GBW), gain frequency product (GFP), and gain transconductance frequency product (GTFP) are studied and analyzed. In this move, at high temperatures, the degradation in analog/RF metrics is observed due to the reduction in carrier mobility. Further, the circuit-level performance is demonstrated at different temperatures. As temperature increases from 250 to 2000 C, 91% and 49% degradation in propagation delay and gain is noticed for inverter, respectively. Further, there is a degradation of 1.6 × in oscillation frequency (fosc ) is noticed for the 3-stage ring oscillator when the temperature increased from 250 to 2000 C. The circuit level performance also deteriorated owing to the degradation of device's performance at higher temperatures. Thus, the analyses will give deep insights into the performance of NSFET at both device and circuit levels at elevated temperatures. [ABSTRACT FROM AUTHOR] more...- Published
- 2023
- Full Text
- View/download PDF
33. Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillator.
- Author
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Chavan, Arunkumar Pundalik and Aradhya, Ravish
- Subjects
PHASE noise ,FREQUENCIES of oscillating systems ,VOLTAGE-controlled oscillators ,MONTE Carlo method ,NONLINEAR oscillators - Abstract
The objective of the proposed work is to demonstrate the use of a hybrid approach for the design of a voltage-controlled oscillator (VCO) which can lead to higher performance. The performance is improved in terms of the tuning range, frequency of oscillation, voltage swing, and power consumption. The proposed hybrid VCO is designed using an active load common source amplifier and current starved inverter that are cascaded alternatively to achieve low power consumption. The proposed VCO achieves a measured phase noise of -74 dBc/Hz and a figure of merit (FOM) of -152.6 dBc/Hz at a 1 MHz offset when running at 5.1 GHz frequency. The hybrid current starved-current starved VCO (CS-CS VCO) consumes a power of 289 µW using a 1.8 V supply and attains a wide tuning range of 96.98%. Hybrid VCO is designed using 0.09 µm complementary metal-oxide-semiconductor (CMOS) technology. To justify the robustness, reliability, and scalability of the circuit different corner analysis is performed through 500 runs of Monte-Carlo simulation. [ABSTRACT FROM AUTHOR] more...
- Published
- 2023
- Full Text
- View/download PDF
34. An oscillator circuit with cross charge and discharge by off-chip capacitors
- Author
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Cao Yang, Cao Zhenji, Cao Liang, and Zhao Guilin
- Subjects
ring oscillator ,charge and discharge of capacitor ,power management chip ,clock ,Electronics ,TK7800-8360 - Abstract
CMOS Ring Oscillator has many advantages such as small layout area, large frequency range and easy integration. It is widely used in the DC-DC buck converter and electronic communication systems. On the basis of the traditional ring oscillator circuit, an independent charge and discharge control path is designed to realize a cross charge and discharge ring oscillator circuit, and a lower frequency oscillation period is obtained by externally connecting an off-chip capacitor. Based on 0.18 μm process, the circuit has been simulated with HSIM tool. After the back-end physical implementation, the layout of the oscillation occupies an area of 172 μm×76 μm. Using tools to extract parasitic parameters from the layout and conduct post-simulation, the simulation results indicates that with externally connecting an off-chip capacitor, and the power supply voltage in 3.3 V and temperature in 25℃, the oscillator has a clock period of 1.2 ms. With the power supply voltage changes in 2.7 V~5.5 V and temperature changes in -55℃~125℃, the frequency deviation is 5.83%.The circuit has been successfully applied in a power management chip. more...
- Published
- 2023
- Full Text
- View/download PDF
35. True Random Number Generator Based on RRAM-Bias Current Starved Ring Oscillator
- Author
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D. Arumi, S. Manich, A. Gomez-Pau, R. Rodriguez-Montanes, M. B. Gonzalez, and F. Campabadal
- Subjects
Hardware security ,non-volatile memory (NVM) ,random number generation ,ring oscillator ,resistive random access memory (RRAM) ,true random number generator (TRNG) ,Computer engineering. Computer hardware ,TK7885-7895 - Abstract
This work presents a resistive random access memory (RRAM)-bias current-starved ring oscillator (CSRO) as true random number generator (TRNG), where the cycle-to-cycle variability of an RRAM device is exploited as source of randomness. A simple voltage divider composed of this RRAM and a resistor is considered to bias the gate terminal of the extra transistor of every current starved (CS) inverter of the ring oscillator (RO). In this way, the delay of the inverters is modified, deriving an unpredictable oscillation frequency every time the RRAM switches to the high resistance state (HRS). The oscillation frequency is finally leveraged to extract the sequence of random bits. The design is simple and adds low area overhead. Experimental measurements are performed to analyze the cycle-to-cycle variability in the HRS. The very same measurements are subsequently used to validate the TRNG by means of electrical simulations. The obtained results passed all the National Institute of Standards and Technology randomness tests (NIST) tests without the need for postprocessing. more...
- Published
- 2023
- Full Text
- View/download PDF
36. A Current-Mode Multiphase Digital Transmitter With a Single-Footprint Transformer-Based Asymmetric Doherty Output Network
- Author
-
Jay R. Sheth, Linsheng Zhang, Xiaochuan Shen, Vinay Iyer, and Steven M. Bowers
- Subjects
Asymmetric Doherty power amplifier (PA) ,CMOS PA ,digital transmitter ,multiphase PA ,poly-phase filter (PPF) ,ring oscillator ,Electric apparatus and materials. Electric circuits. Electric networks ,TK452-454.4 - Abstract
This article introduces a current-mode multiphase digital transmitter with a single-footprint transformer-based asymmetric Doherty output network. The proposed multiphase architecture overcomes the bandwidth expansion associated with the polar power amplifier (PA), while still achieving relatively constant output power and drain efficiency (DE) profiles. Additionally, to achieve efficiency enhancement in deep power back-off (PBO), and to simultaneously achieve a compact form factor, an asymmetric series Doherty output matching network using a transformer-within-transformer structure is also proposed. A proof-of-concept eight-phase digital transmitter using the proposed single-footprint Doherty network is implemented in a general-purpose 65-nm CMOS process. The transmitter achieves more than 20-dBm output power $(P_{\mathrm{ out}})$ and more than 31% DE from 4.5 to 6.7 GHz. At 8-dB PBO, it achieves a DE of 23% and 24% at 6.5 and 7.0 GHz, which corresponds to a $1.76\times $ and $1.93\times $ improvement compared to normalized class B PA, respectively. The transmitter also achieves a 21% DE and an average $P_{\mathrm{ out}}$ of 14 dBm with an r.m.s. error vector magnitude $({\mathrm{ EVM}}_{\mathrm{ rms}})$ of 4.1% for a 20-MSym/s 64-quadrature amplitude modulation waveform at 6.5 GHz. more...
- Published
- 2023
- Full Text
- View/download PDF
37. Creating and balancing the paths of arbiter-based physically unclonable functions on FPGA
- Author
-
A. Yu. Shamyna and A. A. Ivaniuk
- Subjects
physical cryptography ,arbiter-based physically unclonable functions ,symmetrical paths ,propagation delay line ,ring oscillator ,Electronic computers. Computer science ,QA75.5-76.95 - Abstract
Objectives. The problem of constructing a new structure of paths of physically unclonable function of the arbiter type (APUF) on the FPGA is being solved, based on the full use of internal resources of LUT-blocks, which are functionally repeaters. The relevance of the study is associated with the rapid development of physical cryptography tools. Another goal is the developing a methodology for eliminating the asymmetry of the APUF paths associated with the peculiarity of the synthesis of such circuits on the FPGA.Methods. The methods of synthesis of digital devices, their parametric modeling and implementation on rapid prototyping boards are used. A ring oscillator circuit is used to measure the internal propagation delays of signals through the APUF paths.Results. A new structure of the basic element of APUF paths with the use of two functional repeaters is proposed. The necessity of balancing the delays of APUF paths is demonstrated. A technique has been developed to eliminate the asymmetry of signal propagation through APUF paths based on controlled delay lines. The disadvantages of classical approaches as an APUF arbitrator and the need for their modification are shown.Conclusion. The proposed approach to build APUF paths has shown its viability and promise. An improvement in the characteristics of APUF constructed according to the proposed method, as well as a reduction in hardware costs during their implementation compared to classical APUF schemes, is experimentally confirmed. It seems promising to develop the described methodology for constructing the APUF to improve the structure of the arbiter. more...
- Published
- 2022
- Full Text
- View/download PDF
38. A true random number generator with high bit rate and low energy efficiency.
- Author
-
Cheng, Xin, Zhang, Yunfeng, Zhu, Haowen, and Zhou, Yang
- Subjects
- *
RANDOM number generators , *COMPLEMENTARY metal oxide semiconductors , *ENERGY consumption , *BIT rate , *VOLTAGE control , *PHASE coding , *ON-chip charge pumps - Abstract
Summary: In this paper, a novel feedback architecture of true random number generator based on tetrahedral ring oscillator is proposed. The random raw bits are fed back to produce control voltages, which control the transmission gates in ring oscillators. Since random fluctuations of the control voltages increase the phase jitter of the oscillator, this architecture improves the bit rate and randomness of random sequence. Besides, a post‐processor is designed to enhance the randomness further. The circuit is implemented in TSMC 40‐nm complementary metal oxide semiconductor (CMOS) process, and it takes up an area of 85 × 51 μm. Measurement results show that the random number sequences pass the statistical randomness tests, with a low power consumption of 67 μW, high speed of 45 Mbps, and low energy efficiency of 1.48 pJ/bit. [ABSTRACT FROM AUTHOR] more...
- Published
- 2023
- Full Text
- View/download PDF
39. Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits.
- Author
-
Fan, Chenwei, Cheng, Xiaohan, Xu, Lin, Zhu, Maguang, Ding, Sujuan, Jin, Chuanhong, Xie, Yunong, Peng, Lian‐Mao, and Zhang, Zhiyong
- Subjects
INTEGRATED circuits ,TRANSISTORS ,FIELD-effect transistors ,FUNCTIONAL integration ,CHARGE carrier mobility ,CARBON nanotubes - Abstract
Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date. [ABSTRACT FROM AUTHOR] more...
- Published
- 2023
- Full Text
- View/download PDF
40. Oscillator Selection Strategies to Optimize a Physically Unclonable Function for IoT Systems Security.
- Author
-
Aparicio-Téllez, Raúl, Garcia-Bosque, Miguel, Díez-Señorans, Guillermo, and Celma, Santiago
- Subjects
- *
SECURITY systems , *NONLINEAR oscillators , *INTERNET of things , *FIELD programmable gate arrays , *ELECTRIC oscillators - Abstract
Physically unclonable functions avoid storing secret information in non-volatile memories and only generate a key when it is necessary for an application, rising as a promising solution for the authentication of resource-constrained IoT devices. However, the need to minimize the predictability of physically unclonable functions is evident. The main purpose of this work is to determine the optimal way to construct a physically unclonable function. To do this, a ring oscillator physically unclonable function based on comparing oscillators in pairs has been implemented in an FPGA. This analysis shows that the frequencies of the oscillators greatly vary depending on their position in the FPGA, especially between oscillators implemented in different types of slices. Furthermore, the influence of the chosen locations of the ring oscillators on the quality of the physically unclonable function has been analyzed and we propose five strategies to select the locations of the oscillators. Among the strategies proposed, two of them stand out for their high uniqueness, reproducibility, and identifiability, so they can be used for authentication purposes. Finally, we have analyzed the reproducibility for the best strategy facing voltage and temperature variations, showing that it remains stable in the studied range. [ABSTRACT FROM AUTHOR] more...
- Published
- 2023
- Full Text
- View/download PDF
41. Circuit Integration in E-Mode GaN
- Author
-
Kaufmann, Maik Peter, Wicht, Bernhard, Kaufmann, Maik Peter, and Wicht, Bernhard
- Published
- 2022
- Full Text
- View/download PDF
42. A Design and Implementation of Ring Oscillator Physically Unclonable Function Using the Xilinx FPGA
- Author
-
Kulkarni, Swati, Vani, R. M., Hunagund, P. V., Kumar, Amit, Series Editor, Suganthan, Ponnuthurai Nagaratnam, Series Editor, Senatore, Sabrina, Editorial Board Member, Gao, Xiao-Zhi, Editorial Board Member, Mozar, Stefan, Editorial Board Member, Srivastava, Pradeep Kumar, Editorial Board Member, Haase, Jan, Editorial Board Member, Mukherjee, Shyamapada, editor, Muppalaneni, Naresh Babu, editor, Bhattacharya, Sukriti, editor, and Pradhan, Ashok Kumar, editor more...
- Published
- 2022
- Full Text
- View/download PDF
43. Ring Oscillators and Their Design Methodology
- Author
-
Gielen, Georges, Hernandez-Corporales, Luis, Rombouts, Pieter, Gielen, Georges, Hernandez-Corporales, Luis, and Rombouts, Pieter
- Published
- 2022
- Full Text
- View/download PDF
44. Analog VCO Coupling Stages: gm, Source Follower
- Author
-
Gielen, Georges, Hernandez-Corporales, Luis, Rombouts, Pieter, Gielen, Georges, Hernandez-Corporales, Luis, and Rombouts, Pieter
- Published
- 2022
- Full Text
- View/download PDF
45. Time Based and VCO-ADCs from a Signal Processing Perspective
- Author
-
Gielen, Georges, Hernandez-Corporales, Luis, Rombouts, Pieter, Gielen, Georges, Hernandez-Corporales, Luis, and Rombouts, Pieter
- Published
- 2022
- Full Text
- View/download PDF
46. Measurement of the Large-Signal Propagation Delay of Single Transistors
- Author
-
Jenkins, Keith A. and Jenkins, Keith A.
- Published
- 2022
- Full Text
- View/download PDF
47. A Multi-phase LC-Ring-Based Voltage Controlled Oscillator
- Author
-
Das, Sounak, Sen, Subhajit, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Mishra, Biswajit, editor, Mathew, Jimson, editor, and Patra, Priyadarsan, editor more...
- Published
- 2022
- Full Text
- View/download PDF
48. Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits
- Author
-
Chenwei Fan, Xiaohan Cheng, Lin Xu, Maguang Zhu, Sujuan Ding, Chuanhong Jin, Yunong Xie, Lian‐Mao Peng, and Zhiyong Zhang
- Subjects
carbon nanotube ,field‐effect transistors ,monolithic 3D integration ,ring oscillator ,Materials of engineering and construction. Mechanics of materials ,TA401-492 ,Information technology ,T58.5-58.64 - Abstract
Abstract Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date. more...
- Published
- 2023
- Full Text
- View/download PDF
49. A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency.
- Author
-
Kumar, Ravi, Nagulapalli, Rajasekhar, and Vishvakarma, Santosh Kumar
- Subjects
- *
VOLTAGE-controlled oscillators , *PHASE-locked loops , *ELECTRIC oscillators , *ELECTRONIC systems , *POWER resources , *VOLTAGE control - Abstract
Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ( g m ) is the main dominant source of frequency and gain ( K VCO ) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates ≈ 3 times variation in K VCO across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5 GHz is developed in 65 nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum K VCO variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4 mW power from 1 V power supply. [ABSTRACT FROM AUTHOR] more...
- Published
- 2023
- Full Text
- View/download PDF
50. A Tiny Flexible Differential Tension Sensor.
- Author
-
Wieczorek, Piotr Z., Starecki, Krzysztof, Gołofit, Krzysztof, Radtke, Maciej, and Pilarz, Marcin
- Subjects
- *
BAR codes , *NEAR field communication , *FAST moving consumer goods , *RADIO frequency identification systems , *STRAINS & stresses (Mechanics) , *MECHANICAL behavior of materials , *DETECTORS - Abstract
Modern applications of Internet of Things (IoT) devices require cheap and effective methods of measurement of physical quantities. Cheap IoT devices with sensor functionalities can detect a lack or excess of substances in everyday life or industry processes. One possible use of tension sensors in IoT applications is the automated replenishment process of fast moving consumer goods (FMCG) on shop shelves or home retail automation that allows for quick ordering of FMCG, where the IoT system is a part of smart packaging. For those reasons, a growing demand for cheap and tiny tension sensors has arisen. In this article, we propose a solution of a small flexible tension sensor fabricated in an amorphous InGaZnO (a-IGZO) thin-film process that can be integrated with other devices, e.g., near-field communications (NFC) or a barcode radio frequency identification (RFID) tag. The sensor was designed to magnify the slight internal changes in material properties caused by mechanical stress. These changes affect the dynamic electrical properties of specially designed inverters for a pair of ring oscillators, in which the frequencies become stress-dependent. In the article, we discuss and explain the approach to the optimum design of a ring oscillator that manifests the highest sensitivity to mechanical stress. [ABSTRACT FROM AUTHOR] more...
- Published
- 2023
- Full Text
- View/download PDF
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