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We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimentally demonstrate that the new AS provides 15% reduction in the effective capacitance ( ${C}_{{\text {eff}}}{)}$ . Such a ${C}_{{\text {eff}}}$ reduction translates to 21% performance gain at the constant power (iso-power) or 36% power reduction at the constant performance (iso-speed). The benefits provided by AS exceed the benefits of a full CMOS node scaling from 7 to 5 nm. Clearly, AS is a viable technological element for continuing CMOS scaling.

Child welfare agencies and legal authorities have frequently turned to psychologists to conduct parental competency assessments (PCA) to inform decisions aimed to advocate the best interest...

Celiac disease (CD) is a T-cell mediated genetically inherited autoimmune disease affecting approximately 1% of the population. Research suggests that CD impacts executive functioning (EF) and social phobia (SP). However, most of the literature in this area focuses on age groups outside of the traditional college age range and has never measured EF and SP together. This descriptive study compared traditional age female college students with CD to age- and sex-matched college students without CD on measures of EF and SP. Participants completed the Behavior Rating Inventory of Executive Function–Adult version (BRIEF-A), the Social Anxiety Questionnaire for Adults–Short Form (SAQ-A30), and a demographic questionnaire. Results indicated that participants with CD reported lower grade point averages; scored lower on BRIEF-A measures of working memory, planning/organization, and organization of materials; and scored higher on SAQ-A30 measures involving interactions with the opposite sex and strangers. Implications for nursing practice are discussed. [ Journal of Psychosocial Nursing and Mental Health Services, 57 (2), 25–34.]

We report an improved air spacer that is successfully co-integrated on FinFET transistors with Self-Aligned Contacts (SAC) and Contacts Over Active Gate (COAG). The new integration scheme enables air spacer formation agnostic to the underlying transistor architecture, thus paving the way for a seamless adoption of air spacer in FinFET and Gate-All-Around (GAA) technologies. A reduction in effective capacitance $(C_{\mathrm{eff}})$ by 15% is experimentally demonstrated. The power/performance benefits achieved by the new air spacer exceeds the benefits of scaling FinFET from 7nm node to 5nm node.

In this paper, full bottom dielectric isolation (BDI) is first demonstrated on horizontally stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme vs punch through stopper (PTS) scheme has been systematically studied. By comparing off-state leakage current, short channel behavior and effective capacitance (Ceff) for both schemes, we show that BDI could potentially provide: 1) good immunity of sub-channel leakage due to process variation (from parasitic "fat-Fin" which is unique in Nanosheet structure); 2) power-performance co-optimization.

We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO 2 ) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.

In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.

Over 795,000 individuals in the U.S. suffer from strokes annually, with 610,000 accounting for first attacks. Stroke represents the fifth leading cause of death and resulting long-term disability in the United States. Unilateral neglect (UN) is a disabling characteristic of stroke, occurring from lesion damage to one hemisphere of the brain. Individuals with UN do not respond normally to objects, stimuli, and people located to their contralesional side. Right hemispheric lesions exhibit the greatest impairment. Incidence rates of UN vary from 13%-81%. Impairment of this condition impedes an individual's capacity to execute activities of daily living. Diagnosis can be challenging and if left untreated, results in poorer patient outcomes. While standardized test battery covering multiple domains have demonstrated enhanced detection for diagnosis over single test methods, and combination treatment modalities have shown promise in procuring symptom abatement, there is a paucity of evidence on the long-term effects of neglect therapy and its transferability into daily life. Stroke expenditures impose a significant economic encumbrance on healthcare systems with costs estimated at $34 billion per annum in the U.S. alone. Effectively delineating and treating UN would enhance integrated stroke services, improve patient outcomes and reduce the lifetime cost of stroke.

In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at 10nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source / Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.

This paper addresses novel approaches at material and integration fronts for gate applications. Material wise, new n work function metal (WFM) material is explored to address the need for reducing gate resistance and maintaining proper Vt at 20A or less WFM thickness. Integration wise, next generation dipole is tested with various process sequences to address the need in lowering overall thermal budget at the gate level for advanced architectures, such as scaled FinFET and Nanosheets.

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Dielectric thin film spacers play a very important role in defining the silicon channel boundary and junction geometries as well as proximity to silicon stressors and strongly affect key transistor electrical characteristics [1]. Another important application of sidewall spacers is in patterning of 3D FinFETs (Field Effect Transistor), where the Sidewall Image Transfer (SIT) technology [2] helps to overcome the limitations of conventional lithography and to improve control of critical dimensions. Sidewall spacers are also used to control critical dimension (CD) by depositing a spacer film inside a feature to achieve a CD shrink. Tolerance for variability of TFin(Fin width) has to be in the sub nm range to significantly reduce variability in FinFET performance. The need for precise scaling of conventional spacers as well as new patterning applications put very stringent requirements on spacer thin film depositions and on control of spacer film properties during subsequent integration processes. The need for greatly improved spacer process step coverage, tighter thickness control, pattern effects and more stringent film properties requirements strongly influenced the transition from Chemical Vapor Deposition (CVD) to Atomic Layer Deposition (ALD) spacers in the industry. This paper discusses the properties of ALD silicon nitride and silicon oxide spacer films from the perspectives of ALD and MLD (Molecular Layer Deposition) techniques, precursor chemistries and compositional stability after subsequent integration steps like implant anneals and spacer sculpting reactive ion etching processes. Advanced imaging techniques like EELS (Electron Energy Loss Spectroscopy) and XPS (X-ray Photoelectron Spectroscopy) techniques have been used to analyze sidewall spacer transformation. Special attention has been paid to the microloading effect - the dependence of thin film deposition rate on pattern density [3]. Microloading data for CVD, MLD and ALD techniques are compared based on a specially designed microloading measurement vehicle. This is especially useful with geometries needing a sub nm tolerance and when patterning endpoint detection schemes are highly dependent on film properties. The effect of ALD deposition parameters on film electrical characteristics like dielectric breakdown and leakage are also delineated. Silicon strain engineering issues related to the implementation of ALD spacers and techniques aimed at varying and controlling an intrinsic stress level in ALD films are also discussed. The findings helped to optimize the existing ALD/MLD processes for conventional epi and source/drain spacers as well for oxide sidewall ALD spacers for SIT fins patterning and CD shrink on 14nm FinFET technology. References: 1. J-H Yan, J-E Park, L-W Lee, K-S Chu , et.al., VLSI Tech Digest, p.55, (2003) 2. Y-K Choi, T-J King and C. Hu, IEEE Trans. Electron Devices, 49, 3, p.435, (2002) 3. M. Belyansky in ‘Handbook of Thin Film Deposition”, 3rd. Ed., K. Seshan Editor, Elsevier, p.46, (2012)

Treatment fidelity refers to the therapist's actual adherence to treatment procedures, and compatibility refers to the degree to which the therapist's own presuppositions match or conflict with those implicit in the treatment method. In an effort to explore a solution to the problem of achieving treatment fidelity, we hypothesized a correlation between treatment fidelity and compatibility. In participant-therapists, the Therapist Presupposition Inventory (TPI) and the Individualism-Collectivism Scale (ICS) measured compatibility, the predictor. The Fidelity Rating was the criterion. Compatibility predicted fidelity, lending support to our hypothesis. Fidelity ratings correlated with TPI Collectivism scores ranging from .72 to .79, and on the ICS scores ranging from .51 to .73

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Raman spectroscopy has been used as a primary tool to measure silicon strain on shallow trench isolation (STI) test structures. Different STI dielectric gap fill materials have been evaluated as well as the effect of tensile and compressive STI liners on silicon strain. It has been shown that both intrinsic stress of thin film dielectric material and STI structure type affect strain in silicon. Ways of generating high stress in silicon are discussed including the effect of the STI chemical vapor deposition liner material on Si strain. Strain simulation data are found to be in reasonably good agreement with the active area silicon. Advantages and limitations of Raman based strain metrology in the semiconductor industry are delineated. The findings have been confirmed electrically on metal-oxide-semiconductor field effect transistor devices with tensile and compressive strains in the STI region. An improvement in p-type field-effect transistor performance has been demonstrated for silicon on insulator devic...

In the present work, a high aspect ratio process (HARP) using a new O3/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI liners can be implemented. By comparing HARP with HDP, the geometry dependence of nand p-FET performance due to STI stress is discussed

Two experiments were conducted to examine the impact of a defendant’s physical disability on sentencing recommendations in criminal cases. In both experiments, participants were assigned to one of four conditions in a 2 (defendant gender: female, male) x 2 (defendantdisability:wheelchair visible or not) factorial design. Participants in both conditions also completed the Belief in Just World Scale (BJW), the Revised Legal Attitudes Questionnaire (RLAQ), and the Attitudes towards the Criminal Legal System Scale (ATCLS). Participants were then asked to recommend a sentence for the defendant ranging from no period of incarceration to life in prison and to indicate their level of confidence in the recommended sentence. In experiment 1 the defendant was convicted of murder, and in experiment 2 the defendant was convicted of embezzlement. In both experiments, longer sentences were associated with higher scores on the BJW, RLAQ, ATCLS, and male gender. No significant differences were found in recommended sentences for disabled or non-disabled offenders in either condition. Findings suggest that physically disabled offenders are treated no differently than non-physically disabled offenders regardless of defendant gender or type of crime.

Kleine-Levin syndrome (KLS) is a neuropsychiatric sleep disorder primarily affecting adolescent males. Onset is insidious, idiopathic, and hastened by neurological incident or infection. Typically, the initial onset occurs during the teen years or after the second decade, although cases have been documented in early childhood, adulthood, and senescence. KLS is marked by unexpected debilitating, yet reversible, episodic hypersomnia, with varying recurrence rates; cognitive and behavioral impairment; compulsive eating; and feelings of derealization, hypersexuality, apathy, and depressed mood. Diagnosis is problematic due to the syndrome's rarity, disparity of presenting clinical symptoms, and misdiagnosis. Correct diagnosis can take up to 4 years. The clinical course is approximately 8 to 14 years from initial onset, yet may be longer in the adult form of the disorder. KLS has been shown to impact activities of daily living, usurping an adolescent of his/her social relations with peers, experiences, and time. [ Journal of Psychosocial Nursing and Mental Health Services , 54 (3), 41–47.]

Family estrangement, a communication cut-off between family members, remains a neglected topic in the research literature.The purpose of the present study was to establish a prevalence rate of family estrangement, identify precipitating factors leading to estrangement, identify the relationshipsof the estranged relatives, determine the length of the estrangement, and determine the level of stress caused by the estrangement. Data concerning the above factorswere gathered from 354 undergraduate and graduate students. Overall, 154 participants (43.5%) reported experiencing an estrangement; 60 (39%, 16.9% of the entire sample) from 1 or more immediate family members (nuclear estrangement), 94 (61%, 26.6% of the entire sample)from extended family members (extended estrangement). The most frequently cited single causal factor leading to estrangement was a disagreement with the estranged relative in both nuclear and extended estrangements. Participants reporting a nuclear estrangement were estranged from fathers with the greatest frequency. Participants involved in extended estrangements were estranged from aunts and cousins with the greatest frequency. The mean length of estrangement in nuclear estrangements was 59.4 months; 52.8 months in extended estrangements. The level of distress reported by participants was greater in nuclear estrangements. Implications for clinical practice and future research are discussed.

The temperature distribution in an azimuthally symmetric chemical‐vapor‐deposition reactor is calculated at two pressure regimes. Taken into account is the influence of a silicon wafer situated above a uniformly heated susceptor. In the low‐pressure regime, where the mean free path in the gas phase is much greater than the separation between the wafer and susceptor, the wafer is heated solely by radiation. The temperature at the wafer surface can be ∼20% lower than the susceptor temperature and the temperature drop is nearly independent of the thermal conductivity of the surrounding gas. In the high‐pressure regime, where continuum flow exists between the susceptor and the wafer, the later is heated by conduction, convection, and radiation. The temperature at the wafer surface can be ∼10% lower than that of the susceptor and the temperature drop is strongly influenced by the distance separating the wafer and the susceptor, and by the thermal conductivity of the gas. In both pressure regimes, nonuniform te...

In the present work the high aspect ratio process (HARP) using a new O3/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gap fill in sub-65nm CMOS. We prove good gap fill performance up to aspect ratios larger 10:1. Since this fill process doesn't attack the STI liners as compared to HDP, a variety of different STI liners can be implemented

This brief note cautions clinicians about the possibility of adolescents with Conduct Disorder malingering the symptoms of Attention Deficit Hyperactivity Disorder (ADHD) to obtain medication. Presented are some guidelines to consider when the diagnosis of ADHD is indicated in forensic settings with adolescents such as the need for a comprehensive assessment and the importance of exploring the possibility of malingering.

The importance of hardmask technology is becoming increasingly evident as the demand for high-resolution imaging dictates the use of ever-thinner resist films. An appropriately designed etch resistant hardmask used in conjunction with a thin resist can provide the combined lithographic and etch performance needed for sub-100 nm device fabrication. We have developed a silicon-based, plasma-enhanced chemical vapor deposition (PECVD) prepared material that performs both as an antireflective coating (ARC) and a hardmask and thus enables the use of thin resists for device fabrication. This ARC/hardmask material offers several advantages over organic bottom antireflective coatings (BARC). These benefits include excellent tunability of the material's optical properties, which allows superior substrate reflectivity control, and high etch selectivity to resist, exceeding 2:1. In addition, this material can serve as an effective hardmask etch barrier during the plasma etching of dielectric stacks, as the underlying silicon oxide etches eight times faster than this material in typical fluorocarbon plasma. These properties enable the pattering of features in 1-2 μm dielectric stacks using thin resists, imaging that would otherwise be impossible with conventional processing. Potential extendibility of this approach to feature sizes below 100nm has been also evaluated. High resolution images as small as 50nm, have been transferred into a 300nm thick SiO 2 layer by using Si ARC/hardmask material as an etch mask. Lithographic performance and etch characteristics of a thin resist process over both single layer and index-graded ARC/hardmask materials will be shown.

Patterning sub-150 nm features in dielectric stacks using single layer resist processes in conjunction with organic anti-reflective coatings (ARCs) is becoming very difficult. Typical organic ARC-open etch processes suffer from poor ARC-to-resist selectivities (~0.7), and are accompanied by critical dimension (CD) losses. The resist remaining is often not sufficient to prevent artifacts such as substrate microrevicing during subsequent etches. PECVD-Deposited titanium nitride and silicon oxynitride films have been investigated as ARC layers but their basic nature has caused residue formation at the resist/ARC interface. We have developed a PECVD-deposited material, TERA (Tunable Etch-Resistant ARC) that acts as an ARC at 248 nm and 193 nm wavelengths and provides excellent etch selectivity to resist surpassing those attained with organic ARCs. In addition, this material demonstrates excellent hard mask properties for subsequent dielectric etch steps. The optical properties of these films can be easily tuned to minimize substrate reflectance at either imaging wavelength by controlling the precursor composition and deposition conditions. The films are compatible with 248 nm and 193 nm resists - no footing, undercut or residue is observed during patterning. The films can be etched selectively to resist (selectivity ~2.5) that translates to less resist consumption during th ARC-open etch. Compared to resists, TERA demonstrates better etch resistance while patterning dielectric stacks - the silicon oxide-to-TERA Selectivity exceeds 8. In this paper, the excellent optical tunability and substrate reflectivity control achieved with TERA are discussed. Clean lithography using 248 nm, 193 nm and e- beam resists is shown. The etch characteristics of TERA in fluorocarbon and halogen-based plasma chemistries are discussed. Finally, the formation of 135 nm and 120 nm deep trench patterns in thick dielectric stacks using TERA in conjunction with commercial 248 nm and 193 nm resists, respectively is demonstrated. The extendability of this approach to pattern silicon without roughening or microrevicing using sub-200 nm thick resists is motivated.

The bis(tertiary-butylamino)silane-based low-pressure chemical vapor deposition (LPCVD) undoped silicate glass and phospho-silicate glass (PSG) processes were investigated to study film composition, etch rate, and step coverage. Through the addition of phosphorous doping, LPCVD PSG processing offers an attractive low temperature option. Enhanced deposition rate for the PSG process enables the lowering of the deposition temperature to the 400–500 °C range, thereby minimizing the thermal cycle and offering compatibility with many back-end-of-line processes. Many properties of these films are similar to those of the tetraethoxysilane (TEOS)-based LPCVD oxide. Differences in the film properties compared with the TEOS-based LPCVD oxide films can be traced to the composition of these films and the reaction mechanism.

Engineering models, based on computational fluid dynamics, have been developed and used to improve the performance of two metalorganic chemical‐vapor‐deposition reactors. Though the knowledge of the chemical reactions occurring during film deposition is incomplete, the models provide insight into the reactor’s performance and are useful in guiding reactor modifications. In one reactor, the effect of three gas injector designs on the film thickness uniformity is examined; in a second reactor, the shape and placement of a flow deflector, which redistributes the flow of gas over the wafer surface, is studied. In both cases, comparing the experimental results obtained both before and after the reactor modifications, significant improvements in film thickness uniformity were realized.

A description is given of an antenna consisting of an interconnected wire grid formed by etching metallic lines on a dielectric sheet backed by a metallic ground plane. The theory of operation, analytical model, and experimental findings for this approach to a printed array are described. The device is low cost, light weight, and has sufficient bandwidth to be of use in a variety of applications. An analytical model is developed which establishes transmission line equivalent circuits for the wire grid elements. Current distributions determined from the model are shown to predict accurately the measured pattern performance of a typical implementation. The bandwidth as established by various pattern parameters is quantitatively assessed. Particular emphasis is given to methods of amplitude control through control of line impedances. A particular design implementation is presented for a five-wavelength circular array with independent quadrant control. Measured results from this configuration are compared to theory.