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Anyone, anytime, anywhere is the hallmark of OPEN ACCESS publications. This philosophy is serving us well as the IEEE Journal of Electron Devices Society (J-EDS) continues to grow. On January 1st 2013, when J-EDS was launched , I had written to you introducing the five editors constituting the founding editorial board of the nascent J-EDS. At that time, I had also stated that the board will be expanded as the manuscript submission rate climbs. At this time, the editorial board is being doubled in size by adding five additional members. These professionals are established senior researchers in the field of electron devices and widely respected in their areas of specialty. They have been handpicked to reflect the J-EDS editorial culture of proactively helping authors publish their best work in the journal. As mentioned in my January 2013 editorial , “In a sense, the editor is to assume a supportive role in helping the author improve the quality of the manuscript rather than simply passing a judgment.”

Experimental and simulation results of high-frequency channel noise in MOSFETs with 40-, 80-, and 110- nm gate lengths are presented. The measured dc I-V characteristics can be matched using the drift-diffusion (DD) and hydrodynamic (HD) transport models, both incorporating velocity saturation. The DD model grossly underestimates the measured noise, demonstrating the inadequacy of channel-length modulation and impact ionization to explain the excess noise. The HD model generates higher noise but not enough, showing that introduction of carrier heating is still insufficient to explain the experimental results. The underprediction of noise using the HD model can be mitigated by a suitable choice of the energy relaxation time and saturation velocity; however, simultaneous matching of both noise and dc I-V does not produce satisfactory results. Thus, TCAD simulators are unable to simulate this excess-noise mechanism at this time. Experimental data support that, at 40 nm gate lengths, noise can be described by a shot noise like expression.

Analytical expressions for channel thermal noise and induced-gate noise considering mobility degradation and carrier heating in the non-quasi-static regime are presented. At a given frequency, as a function of channel electric field, channel thermal noise current increases for pure carrier heating and decreases for pure mobility degradation. With both effects present, the increase in noise is much slower and under quasi-static approximation, based on the model used, the two effects cancel out. Induced-gate current noise, on the other hand, increases when both effects are present. Individual presence of either of the two short-channel effects produces similar but slower increase. A physical explanation for the above behavior is presented. An elemental analysis for long-channel devices reveals that, under device saturation, thermal voltage fluctuations precisely at a distance (5/9)L eff from the source, do NOT produce any induced-gate current noise.

Classical active transmission-line analysis of channel thermal noise and induced-gate noise in a MOSFET is extended to include non-quasi-static effects. For long-channel MOSFETs this results in simple analytical expressions exhibiting a frequency-squared correction to channel thermal noise, a fourth power in frequency correction to induced-gate noise and a new real part to the correlation coefficient between the two varying linearly with frequency. Using the channel segmentation approach the results are verified using Spice simulations. The expressions can be extended to include the induced substrate current noise and incorporated in compact models.

A physical understanding of both intrinsic and extrinsic noise mechanisms in a MOSFET is developed. Intrinsic noise mechanisms fundamental to device operation include channel thermal noise, induced gate noise, and induced substrate noise. While the effect of channel thermal noise is observable at zero drain-to-source voltage, the induced gate and substrate noise do not manifest themselves under these conditions. However, the attendant fluctuations in the channel charge are observable by the passage of electric current through the device. Extrinsic noise mechanisms manifested due to structural evolution of the MOSFET include the distributed gate resistance noise, distributed substrate resistance noise, bulk charge effects, substrate current supershot noise, gate current noise, excess channel noise, and 1/f noise. Where available, compact noise models covering these noise mechanisms are explained. Also, where possible, methods of suppression of these mechanisms are highlighted. A survey of current public domain MOS models is presented, and a lack of comprehensive coverage of noise models is noted. Open areas of MOSFET noise research in the sub-hundred-nanometer regime are also highlighted. With suitable adaptation, noise concepts elucidated in the context of MOS transistors have a much wider applicability to the operation of HEMTs, JFETs, MESFETs, and other field-effect devices

An improved model to predict sensitivity of p-i-n lightwave receivers using CMOS technology is proposed. This model incorporates the latest understanding of excess channel noise observed in nanoscale MOSFETs. For the case of an ideal channel filter, the results are presented in an analytical closed form. For nonideal channels, the concept of higher order Personick integrals is introduced. Up to 10 Gb/s, the results predicted by the above model closely mimic the existing CMOS data published over the last 20 years. Above 10 Gb/s, due to lack of CMOS data, projections are evaluated against the nonsilicon technologies. The predictions compare very favorably with the measured system performance using high electron mobility transistors and heterojunction bipolar transistors. The findings thus indicate that CMOS should claim its status as the low-cost high-performance highly integrated technology of choice for lightwave applications beyond 10 Gb/s.

A normalized analytical solution for the capacitance associated with a MOSFET surface under non-equilibrium conditions is presented. It is shown that this model can be mapped into an equivalent equilibrium problem with 98% accuracy for near intrinsic samples (UB ≅ 2). The precision becomes even better for highly doped semiconductors. The physics behind this transformation is explained and nomograms generated to present data in a highly normalized form.

We propose a method to determine the absolute location of energy levels when electrical contact is made between two dissimilar materials. The conventional method of determining the energy levels is correct only as a limiting case when the number of electrons in one sample greatly exceed that in the other.

According to classical theories, a MOS transistor with zero source-to-drain voltage behaves like a passive resistor exhibiting channel thermal noise and the effect of induced gate noise vanishes. Here, we show that the effect of induced gate noise persists as conductance fluctuations even under these "equilibrium" conditions without disturbing the Nyquist relationship governing the channel thermal noise.

Due to ever increasing demands on his time, Prof. Mehdi Anwar is moving on from the editorial board of J-EDS. As a member of the founding Editorial Board I want to thank Mehdi for his support in the formative years of the publication. He did an excellent job in enforcing the highest standards of quality of the finished manuscripts while at the same time lending a helping hand to the authors. This spirit has been the hallmark of J-EDS since its inception in 2013. Mehdi we wish you all the best in your future endeavors.

Progress in the design of high performance photodetectors has been reviewed. On the basis of a general fluctuation theory, seemingly disjoint activities in this area are demonstrated to be of common origin. The conventional wisdom of designing low-noise photodetectors by using single species multiplication processes is compared with new approaches. Also, the noninstantaneous nature of the response to a photon is demonstrated to be not only useful but leading to near ideal amplification. The interplay between the evolution of new concepts, material limitations and performance requirements is elucidated. >

Magnitude of the signal relative to noise determines the ultimate quality of all information transmission. In a lightwave system, there are several fundamental and nonfundamental noise mechanisms that govern the system performance. In this paper, concepts related to these issues will be developed and a review of the current status of this rapidly evolving field will be given.

High-frequency simulations of channel-thermal noise in MOSFETs with gate-lengths of 40 nm, 80 nm, and 110 nm are presented. The simulated noise parameter γ is a stronger function of the carrier transport model at shorter gate-lengths. Velocity saturation is necessary to produce a good match between the simulated and measured DC I-V characteristics using either the drift-diffusion or hydrodynamic transport models. However, in the presence of velocity saturation, the simulated noise is insufficient in explaining the observed excess noise. Hence, these physics-based device-level simulations point to the presence of a non-thermal RF noise source in the FET channel.

High-Frequency signal and noise measurements on 40 nm, 80 nm, and 110 nm, gate-length MOS transistors are performed. On-wafer measurements of S-parameters up to 18 GHz yield an accurate small-signal RF device model with g 2 in excess of 1000 mS/mm. Noise contributions due to gate resistance, substrate resistance, source and drain resistances, substrate current and induced-gate noise are found to be small in comparison with total observed noise. The noise parameter γ is bias dependent and increases as channel-length decreases. The observed values are well above the ideal value of 2/3 consistent with previously published results.

A physical understanding of both intrinsic and extrinsic noise mechanisms in an IGFET is developed. Intrinsic noise mechanisms fundamental to device operation include channel thermal noise, induced gate noise and induced substrate noise. While the effect of channel thermal noise is observable at zero drain-to-source voltage, the induced gate and substrate noise do not manifest themselves under these conditions. However, the attendant fluctuations in the channel charge are observable by the passage of electric current through the device. Extrinsic noise mechanisms manifested due to structural evolution of the MOSFET include the distributed gate resistance noise, distributed substrate resistance noise, bulk charge effects, substrate current super-shot noise and gate current noise. Where possible, methods of suppression of these mechanisms are also highlighted.

Sitting on the third floor of the Princeton Public Library, Princeton NJ, USA, the hometown of Albert Einstein, I was conducting the business of IEEE Journal of Electron Device (J-EDS). While on the J-EDS website, I noted an interesting statistic. The impact factor of J-EDS was 2.472. In simple language this means that on an average, a paper published in J-EDS, since its inception in 2013, has been cited 2.5 times in the literature. While this may not sound like a large number, let me present some comparisons. The current impact factor of IEEE Transactions on Electron Devices (T-ED) is 2.512, exceeding that of J-EDS by 0.04. Thus over a short span of two years since its birth [1] , thanks to the patronage of authors and readers alike, coupled with the hard work of the editorial board, the J-EDS is now approaching the performance metric of its big brother T-ED. To provide a further comparison, I dug up my December 1994 presentation to the IEEE Electron Devices Society (EDS) Administrative Committee (ADCom) and found that Electron Device Letters (EDL), over the same first two years of its life, had an impact factor of 0.42 back in 1982. Thus the growth pattern of J-EDS has been nothing but spectacular. The gap with highly successful sister publications such as the IEEE Journal of Photovoltaics [2] with an impact factor of 3 is closing.

This paper presents experimental results to quantify the impact of UWB on the performance of IEEE 802.11a wireless LAN operated in line-of-sight environment. Interferer and receiver antennas were located in close proximity. Multipath interference was minimized by operating the system outdoors, forcing wave propagation parallel to the ground plane. Results indicate a significant impact on the S/N ratio, frame and data errors and packet lengths. A severe drop in data rates and throughput was also observed. A new parameter to better quantify WLAN performance is proposed.

A cascade of 8 gain-controlled stages providing a maximum gain of 50dB and a 70dB dynamic range will be reported A 900MHz bandwidth has been attained in an NMOS chip employing 0.75μm gate lengths, with a power dissipation of 250mW.

In September 1999, this author published an editorial (ibid., vol. 46, no. 9, p. 1817, Sep. 1999) in IEEE Transactions on Electron Devices (T-ED) emphasizing the need for authors to pay special attention while referencing previously published related information. As mentioned at that time, omitting related work is not only unfair to researcher(s) who have made earlier contributions to the field but it also gives a distorted view of the topic to the reader. More importantly, it demonstrates an author??s lack of knowledge of prior art in their area of research. Hence, there may be significant room for improvement in the technical quality of the manuscript. Since then, we have continually sensitized the authors to this important issue before adopting the following measures. Every year, the Electron Devices Society (EDS) confers its prestigious Paul Rappaport and the more recent George Smith (2002) Awards for best papers published in our flagship publications IEEE T-ED and IEEE Electron Device Letters (EDL), respectively. To reward proper citation philosophy in EDS publications, we have now instituted clear guidelines to take this factor into account in the paper selection process for these awards. Also, we have tightened up the manuscript review process for both T-ED and EDL to make incomplete citations as grounds for rejection.

Summary form only given, as follows. The editorial boards of the IEEE Transactions on Transactions on Electron Devices (T-ED), IEEE Transactions on Electron Device Letters (EDL), and the IEEE JOURNAL OF THE Electron Devices Society (J-EDS) have taken note of a substantial increase in device-oriented manuscripts focused on a variety of "emerging technologies" and, as such, do not fall into traditional subject categories utilized by our journals. Examples include novel nanoelectronic and nanophotonic devices based on various "low-dimensional" material systems such as graphene sheets, nanoribbons, carbon nanotubes, transition metal dichalcogenides, and topological insulators, etc. In recognition of this important trend, and in order to best serve the Electron Devices Society community, we announce the formation of an "Emerging Technologies and Devices" category within T-ED, EDL, and J-EDS, with specific editors assigned to this topic. We recognize that a category with a title of "emerging" by definition represents a dynamic situation (today's emerging device may well become tomorrow's mainstream device), but it is a terminology easily understood by practitioners of our field. This category will cover the physics, modeling, and operation of such low-dimensional devices, as well as the fabrication techniques needed to construct them, and will begin with the February 2013 issue.

The purpose of this note is to bring to your attention a trend that has emerged. The gap between authors/institutions that promise to honor the page charge and the subset that actually ends up honoring them is on the rise. While the page charge, as mentioned earlier, is not mandatory, from the budgetary perspective, it is imperative that your response accurately reflects your intentions. We would like to remind the authors and their sponsoring institutions that the page charge is a legitimate research investment and hence needs to be part of any R&D proposal. It is in this spirit that we appeal to you to honor all page charges and keep this in mind the next time you respond to a page charge query. If there is anything that we can do to help in this process, please let us know. As always, we appreciate your feedback.

It has been a long-standing practice of the IEEE Electron Devices Society to treat all manuscripts submitted for publication to our journals as privileged information. This information is provided to reviewer(s) solely to assess the quality of the submission for publication. Hence, the sharing of the contents of the manuscript for informational purposes outside or even within one's organization is strictly prohibited. In the event that the designated reviewer is unable or unwilling to review the submission, the designee may pass on the manuscript, for review only, to a professional colleague. A corollary to the privacy of manuscripts is the privacy of reviews themselves. Reviews are also confidential communications provided to the author(s) for the sole reason of giving feedback regarding the technical and other publishing aspects of the manuscript. Hence, the sharing of these reviews is also an inappropriate use of information. Please note that members of the editorial board are also required not to share either the manuscript or the reviews with anyone except with individuals involved in the editorial process. While the reasons for treating both aspects of the review process as confidential may be different, the goal is to make the process fair and equitable. The purpose of this announcement is to sensitize all stakeholders to these practices to promote strict adherence. Please note that the responsibility of compliance lies solely with technical professionals, editors, reviewers, and authors alike and not with their respective organizations. Submission, reviewing, and handling of a manuscript will be interpreted as an implied consent to the above.

The author presents an historical review of the development of IEEE Transactions on Electron Devices from 1990 to 2000. The paper covers the tool building phase and the system execution phase of the development.

Summary form only given, as follows. In March 1876, the now famous words "Mr. Watson - come here - I want to see you" uttered by Alexander Graham Bell launched wired telephony in the United States. Over time, America was criss-crossed by POTS (plain-old-telephone service) lines. Ironically, although the US was in the forefront of this wired telephone revolution, it lagged behind in large-scale deployment of the wireless telephony. Nations worldwide jumped ahead making widespread use of cellular telephony much earlier by simply installing communication towers and becoming connected by wireless overnight. The reason for this is that, however primitive it may be, it is difficult to displace an existing technology that works. A parallel can be drawn between this and the manuscript handing process for publications of the Electron Devices Society. Back in the early 90?s, we were in the lead in IEEE, computerizing the handling of manuscripts using primitive DOS-based applications running on the newborn personal computer. We refined this system over time and delayed the cut-over to web-based systems waiting for the technology to mature. We believe that the time is now ripe to make this transition. Starting January 1st, 2008, we have started processing all submissions to Electron Device Letters using IEEE?s web-based "Manuscript Central Author Submission and Peer Review System." To submit manuscripts using this system, please visit http://mc.manuscriptcentral.com/edl. In accordance with this new system, please DO NOT send manuscripts directly to the Editor-in-Chief or to the Publications Office. Your submitted manuscript will now be accessed via the Manuscript Central.We welcome any suggestions you may have to make this system more user-friendly, efficient and versatile.

The purpose of this note is to bring to your attention a trend that has emerged. The gap between authors/institutions that promise to honor the page charge and the subset that actually ends up honoring them is on the rise. While the page charge, as mentioned earlier, is not mandatory, from the budgetary perspective, it is imperative that your response accurately reflects your intentions. We would like to remind the authors and their sponsoring institutions that the page charge is a legitimate research investment and hence needs to be part of any R&D proposal. It is in this spirit that we appeal to you to honor all page charges, and keep this in mind the next time you respond to a page-charge query. If there is anything that we can do to help in this process, please let us know. As always, we appreciate your feedback.

IEEE Electron Device Letters was launched under the leadership of George E. Smith by the IEEE Electron Devices Society in January 1980. It was instituted to fulfill the need for a peer-reviewed quick-turnaround publication. Traditionally, the society has recognized the best paper published in two of our flagship publications, IEEE Electron Device Letters (EDL) and IEEE Transactions on Electron Devices (T-ED) through the Paul Rappaport Award. Over these years, however, although EDL papers have been nominated for this award, they have never made it to the finish line. The reason for this has been that short EDL papers cannot compete favorably against full-length T-ED contributions.We have now taken measures to correct this inequity. I am delighted to announce that the Electron Devices Society and IEEE Technical Advisory Board have approved a special award to recognize papers published in EDL. This award is being named after the founding Editor-in-Chief, George E. Smith. It will be given for the first time in December 2003 at the IEDM in Washington, DC, for the best paper published in calendar year 2002. Apart from technical excellence, an important criterion for selecting the best paper is a clear enunciation of the merit of a contribution in relation to prior art. Hence, authors are encouraged to take the time to look up relevant work already published by researchers in institutions worldwide, especially work other than their own. This will improve the quality of their submission and that of our journal. We intend to sensitize authors to this issue across all EDS-sponsored and co-sponsored publications. This will create the healthy environment where prior knowledge is leveraged to the fullest extent, shortening research and development cycles and accelerating the pace of knowledge creation. Also, it will result in proper credit being given where it is due. This should be a win-win situation for everyone involved.

Current high-speed device structures have carriers traveling across submicrometer device dimensions under the influence of extremely high electric fields. This gives rise to avalanche multiplication in a finite medium with only a few ionizing collisions per traversal of the primary carrier through the device. The finite medium avalanching results in less uncertainty in the gain process and hence a promise of low-noise avalanche multiplication.

The noise manifested by impact-ionization-generated substrate current in fine-line NMOS transistors is studied. It is found that this noise can be considerably above the shot noise level for high drain voltages. The magnitude of this noise is interpreted in terms of an avalanche gain produced by a multistep impact-ionization process involving both holes and electrons. The device structure imposes one positive and one negative feedback loop and exhibits a peak in the noise as a function of the drain voltage.

The effect of measurement time and the detection system bandwidth product in determining the signal‐to‐noise ratio is formulated. Results are derived for both cases when the detector is operated in the deterministic limit and the random limit. A comparison suggests that for level detection, when the measurement accuracy is limited by the finite time constant of the detection system, the random limit operation results in superior performance. For pulse detection, the random limit operation makes it possible to approach the ideal performance limit for large time bandwidth products. Also, the random scheme can attain the ideal performance limit even in the presence of gain fluctuations of the detector. The principle of random multiplication therefore provides an alternative approach to realizing ideal photodetectors.

An equilibrium solution is presented for the semiconductor surface in terms of the potential, electric field, charge density, and change in mobile‐carrier concentrations throughout the semiconductor as a function of the surface potential and bulk doping. These results are an extension of the work initiated by R. H. Kingston and S. F. Neustadter [J. Appl. Phys. 26, 718 (1955)]; and extended by C. E. Young [J. Appl. Phys. 32, 329 (1961)]. The present results cover a wider range of all the parameters involved in the problem; also, through quantities chosen for normalization and through choice of origin, the present results remove a considerable redundancy existing in the previous data. Finally, the identity of the equilibrium surface problem and the equilibrium step‐junction problem is demonstrated and explained.

Receiver design noise considerations for FET front ends for fiber-optics amplifiers as presented by Smith and Personick are revisited. The MOSFET noise model used is simple yet more accurate than that used previously. The device equivalent circuit for noise is derived from first principles. We are thus able to optimize the amplifier sensitivity with respect to hot-carrier channel thermal noise in terms of the FET drain-to-source voltage and the effective channel length. The importance of drain-source overlap capacitance in determining amplifier sensitivity, which has hitherto not been formulated, is also quantified. It is thus concluded that in spite of hot-carrier noise effects, fine-line NMOS amplifiers designed for gigabit-rate applications will continue to see sensitivity improvement for effective channel lengths down into the quarter-micrometer range. Investigation in the subquarter-micrometer range is in progress.

Acoustic mode lattice scattering plays an important role in determining the carrier mobility in elemental semiconductors over a wide range of temperature. For germanium and silicon, over the temperature range of interest, these longitudinal acoustic phonons are primarily scattered by isotopes and chemical impurities. The relaxation time is directly proportional to the fourth power of the phonon wavelength. Hence, for a relatively small phonon wavelength spread of three decades, the phonon relaxation time spans full 12 decades. The number of phonons for a given acoustic mode fluctuates at random. Hence, the phonon population for each mode exhibits a g‐r noise spectrum characterized by its relaxation time. Through electron‐phonon interaction (assuming elastic scattering), this g‐r noise spectrum is transferred to electron mean free path (same holds for hole), where after superposition, it leads to 1/f spectrum. The theoretical results support the experimental findings of several authors.