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Graph states are a class of important multiparty entangled states, of which bell pairs are the special case. Realizing a robust and fast distribution of arbitrary graph states in the downstream layer of the quantum network can be essential for further large-scale quantum networks. We propose a novel quantum network protocol called P2PGSD inspired by the classical Peer-to-Peer (P2P) network to efficiently implement the general graph state distribution in the network layer, which demonstrates advantages in resource efficiency and scalability over existing methods for sparse graph states. An explicit mathematical model for a general graph state distribution problem has also been constructed, above which the intractability for a wide class of resource minimization problems is proved and the optimality of the existing algorithms is discussed. In addition, we leverage the spacetime quantum network inspired by the symmetry from relativity for memory management in network problems and used it to improve our proposed algorithm. The advantages of our protocols are confirmed by numerical simulations showing an improvement of up to 50% for general sparse graph states, paving the way for a resource-efficient multiparty entanglement distribution across any network topology.

A subset of vertices in a graph $G$ is considered a maximal dissociation set if it induces a subgraph with vertex degree at most 1 and it is not contained within any other dissociation sets. In this paper, it is shown that for $n\geq 3$, every unicyclic graph contains a minimum of $\lfloor n/2\rfloor+2$ maximal dissociation sets. We also show the graphs that attain this minimum bound., Comment: 13 pages, 7 figures

Quantum computing hardware is affected by quantum noise that undermine the quality of results of an executed quantum program. Amongst other quantum noises, coherent error that caused by parameter drifting and miscalibration, remains critical. While coherent error mitigation has been studied before, studies focused either on gate-level or pulse-level -- missing cross-level optimization opportunities; And most of them only target single-qubit gates -- while multi-qubit gates are also used in practice. To address above limitations, this work proposes a cross-layer approach for coherent error mitigation that considers program-level, gate-level, and pulse-level compiler optimizations, by leveraging the hidden inverse theory, and exploiting the structure inside different quantum programs, while also considering multi-qubit gates. We implemented our approach as compiler optimization passes, and integrated into IBM Qiskit framework. We tested our technique on real quantum computer (IBM-Brisbane), and demonstrated up to 92% fidelity improvements (45% on average), on several benchmarks.

Kochol introduced the assigning polynomial $F(G,\alpha;k)$ to count nowhere-zero $(A,b)$-flows of a graph $G$, where $A$ is a finite Abelian group and $\alpha$ is a $\{0,1\}$-assigning from a family $\Lambda(G)$ of certain nonempty vertex subsets of $G$ to $\{0,1\}$. We introduce the concepts of $b$-compatible graph and $b$-compatible broken bond to give an explicit formula for the assigning polynomials and to examine their coefficients. More specifically, for a function $b:V(G)\to A$, let $\alpha_{G,b}$ be a $\{0,1\}$-assigning of $G$ such that for each $X\in\Lambda(G)$, $\alpha_{G,b}(X)=0$ if and only if $\sum_{v\in X}b(v)=0$. We show that for any $\{0,1\}$-assigning $\alpha$ of $G$, if there exists a function $b:V(G)\to A$ such that $G$ is $b$-compatible and $\alpha=\alpha_{G,b}$, then the assigning polynomial $F(G,\alpha;k)$ has the $b$-compatible spanning subgraph expansion \[ F(G,\alpha;k)=\sum_{\substack{S\subseteq E(G),\\G-S\mbox{ is $b$-compatible}}}(-1)^{|S|}k^{m(G-S)}, \] and is the following form $F(G,\alpha;k)=\sum_{i=0}^{m(G)}(-1)^ia_i(G,\alpha)k^{m(G)-i}$, where each $a_i(G,\alpha)$ is the number of subsets $S$ of $E(G)$ having $i$ edges such that $G-S$ is $b$-compatible and $S$ contains no $b$-compatible broken bonds with respect to a total order on $E(G)$. Applying the counting interpretation, we also obtain unified comparison relations for the signless coefficients of assigning polynomials. Namely, for any $\{0,1\}$-assignings $\alpha,\alpha'$ of $G$, if there exist functions $b:V(G)\to A$ and $b':V(G)\to A'$ such that $G$ is both $b$-compatible and $b'$-compatible, $\alpha=\alpha_{G,b}$, $\alpha'=\alpha_{G,b'}$ and $\alpha(X)\le\alpha'(X)$ for all $X\in\Lambda(G)$, then \[ a_i(G,\alpha)\le a_i(G,\alpha') \quad \mbox{ for }\quad i=0,1,\ldots, m(G). \], Comment: 12pages

Circuit knitting emerges as a promising technique to overcome the limitation of the few physical qubits in near-term quantum hardware by cutting large quantum circuits into smaller subcircuits. Recent research in this area has been primarily oriented towards reducing subcircuit sampling overhead. Unfortunately, these works neglect hardware information during circuit cutting, thus posing significant challenges to the follow on stages. In fact, direct compilation and execution of these partitioned subcircuits yields low-fidelity results, highlighting the need for a more holistic optimization strategy. In this work, we propose a hardware-aware framework aiming to advance the practicability of circuit knitting. Drawing a contrast with prior methodologies, the presented framework designs a cutting scheme that concurrently optimizes the number of gate cuttings and SWAP insertions during circuit cutting. In particular, we leverage the graph similarity between qubits interactions and chip layout as a heuristic guide to reduces potential SWAPs in the subsequent step of qubit routing. Building upon this, the circuit knitting framework we developed has been evaluated on several quantum algorithms, leading to reduction of total subcircuits depth by up to 64% (48% on average) compared to the state-of-the-art approach, and enhancing the relative fidelity up to 2.7$\times$., Comment: Accepted to the 2024 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24)

Recently, large language models (LLMs) have shown remarkable capabilities including understanding context, engaging in logical reasoning, and generating responses. However, this is achieved at the expense of stringent computational and memory requirements, hindering their ability to effectively support long input sequences. This survey provides an inclusive review of the recent techniques and methods devised to extend the sequence length in LLMs, thereby enhancing their capacity for long-context understanding. In particular, we review and categorize a wide range of techniques including architectural modifications, such as modified positional encoding and altered attention mechanisms, which are designed to enhance the processing of longer sequences while avoiding a proportional increase in computational requirements. The diverse methodologies investigated in this study can be leveraged across different phases of LLMs, i.e., training, fine-tuning and inference. This enables LLMs to efficiently process extended sequences. The limitations of the current methodologies is discussed in the last section along with the suggestions for future research directions, underscoring the importance of sequence length in the continued advancement of LLMs., Comment: Accepted to IJCAI 2024 Survey Track -- camera-ready version

Quantum error-correcting codes (QECCs) can eliminate the negative effects of quantum noise, the major obstacle to the execution of quantum algorithms. However, realizing practical quantum error correction (QEC) requires resolving many challenges to implement a high-performance real-time decoding system. Many decoding algorithms have been proposed and optimized in the past few decades, of which neural network (NNs) based solutions have drawn an increasing amount of attention due to their high efficiency. Unfortunately, previous works on neural decoders are still at an early stage and have only relatively simple architectures, which makes them unsuitable for practical QEC. In this work, we propose a scalable, fast, and programmable neural decoding system to meet the requirements of FTQEC for rotated surface codes (RSC). Firstly, we propose a hardware-efficient NN decoding algorithm with relatively low complexity and high accuracy. Secondly, we develop a customized hardware decoder with architectural optimizations to reduce latency. Thirdly, our proposed programmable architecture boosts the scalability and flexibility of the decoder by maximizing parallelism. Fourthly, we build an FPGA-based decoding system with integrated control hardware for evaluation. Our $L=5$ ($L$ is the code distance) decoder achieves an extremely low decoding latency of 197 ns, and the $L=7$ configuration also requires only 1.136 $\mu$s, both taking $2L$ rounds of syndrome measurements. The accuracy results of our system are close to minimum weight perfect matching (MWPM). Furthermore, our programmable architecture reduces hardware resource consumption by up to $3.0\times$ with only a small latency loss. We validated our approach in real-world scenarios by conducting a proof-of-concept benchmark with practical noise models, including one derived from experimental data gathered from physical hardware., Comment: 12 pages, 16 figures