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A magnitude phase-locked loop (MPLL) is a system that synchronizes its output signal in frequency, phase, and magnitude with the dominant sinusoidal component of its input signal. We propose a novel MPLL design based on the model of a synchronverter [i.e., an inverter that behaves toward the power grid like a synchronous generator (SG)]. The synchronverter model is detached from its usual three-phase power electronics environment and transformed into a (single phase) MPLL with a wide pull-in range and great noise rejection properties. We prove synchronization under reasonable conditions. Extensive simulation results are provided to validate its performance and to compare it with existing solutions.

Virtual synchronous machines (VSMs) are inverters that behave toward the power-grid-like synchronous generators. Hence, they can be used as grid-forming inverters, and they can support the grid with inertia, droops, fault ride-through, and more. Synchronverters are a much studied type of VSMs. In this article, we present several improvements and innovations to the synchronverter control algorithm. We offer a complete design procedure for this algorithm. One change is meant to mitigate the fact that earlier designs are very sensitive to grid voltage measurement errors and processing delay, which may cause harmonic distortion and fluctuating amplitude of the grid-side currents. We propose to include a fast current controller as the internal control loop of the inverter. The design of this current controller involves delicate issues of compensating the delays and eliminating the dc components of the currents. The new design also enables a natural way for distortionless current limitation. We present a smooth start-up procedure. Our simulations and experiments show that the current controller leads to a dramatic reduction of the sensitivity of the VSM to measurement errors, processing delay, and grid voltage imbalance