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A promising class of optical filters is introduced, based on diffraction at small apertures. The filters consist of straight pores with diameters in the micrometer regime and a length of up to one millimeter through a silicon wafer. In contrast to Bragg, Woods, or glass filters, the light is not transmitted in matter but in the medium inside the pores. The filters therefore show a true shortpass characteristic. Due to constructive interference between the high number of pores in an array, macropore filters are of high optical quality and may replace conventional filters in imaging systems.

A large-area MOS-controlled thyristor (MOS-GTO) has been realized by introducing a new wafer-scale repair technique. The large-area device has a diameter of 3 cm. It has been contacted with an IC-compatible pressure contact and has been fabricated on a lowly doped n-type substrate suitable for very-high-voltage applications comparable to conventional GTOs. The snubbered and unsnubbered turn-off currents were 400 and 200 A, respectively. The currents could be switched up to a final anode-to-cathode voltage of >1500 V. The unique turn-off capabilities have been achieved by an improved design of the MOS-controlled emitter cell. The main feature of the new cell design is an integrated emitter series resistor, which avoids current filamentation during turn-off. In addition an n/sup +/ buried layer underneath the source of the MOS-controlled emitter cell has been used to reduce the parasitic action of the MOS part of the emitter cell during the on-state. >

▪ Abstract When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical devices. The basics of wafer-bonding technology are described, including microcleanroom approaches, prevention of interface bubbles, bonding of III-V compounds, low-temperature bonding, ultra-high vacuum bonding, thinning methods such as smart-cut procedures, and twist wafer bonding for compliant substrates. Wafer bonding allows a new degree of freedom in design and fabrication of material combinations that previously would have been excluded because these material combinations cannot be realized by the conventional approach of epitaxial growth.

High-speed digital ICs as decision circuits, time-division multiplexers (MUX), demultiplexers (DEMUX), and frequency dividers are key components for multigigabit-per-second optical-fiber links. While advanced silicon bipolar technology meets the demands for all electronic components of 10-Gb/s direct detection transmission links now in development, there is a question whether the situation will change at transmission rates of 20 Gb/s. The authors try to answer this question by presenting the above key components with record operating speeds. A silicon bipolar technology with selective epitaxial growth (SEG) of the active base and collector regions is used for circuit fabrication. A static 16:1 low-power frequency divider demonstrates the low-power capability of the SEG technology. All measured data rates and frequencies are significantly higher than reported values for silicon ICs and, with one exception, even for III-V ICs. The 40 Gb/s measured with the DEMUX is the highest data rate achieved with an IC in any technology. >

A high performance, selfaligned bipolar transistor has been developed by usin the SEG (Selective Epitaxial Growth) technology. Key ? eatures of the SEG-transistor are an extremely shallow, active collector depth in conjunction with a diffused arsenic buried layer exhibiting a thickness of only 450nm and a transition sharpness of about 50nm over two doping decades. CML-ringoscillators with minimum gate delays of 26ps were fabricated with devices showing a measured cutoff frequency (fT) of 32.5 GHz.

Static frequency dividers have been fabricated in a selective epitaxial bipolar technology using 0.8 mu m lithography. The measured maximum frequency of 25 GHz is the highest value reported for static silicon dividers. Moreover, a 16 GHz low-power version is presented which consumes only 8 mW in the first stage.

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.

Unbonded areas or bubbles generated at the interface of bonded silicon wafers in the temperature range of 200-800°C have been investigated. Experiments described in this paper demonstrate that the desorption of hydrocarbon contamination at the silicon wafer surfaces appears to be a necessary condition for the formation of these bubbles. SIMS data also indicate the existence of hydrocarbons at the bonding interface. It is speculated that hydrocarbon gas such as CH4 is required for bubble nucleation and that either CH4 or H2 itself or a mixture of both gases is contained in these bubbles. Finally, methods to prevent the formation of these bubbles are presented.

A method of fabricating micrometre-sized field emission diodes is described. The devices use silicon field emitters that have been grown by selective epitaxy into 0.9 μm sized contact holes in a 1 μm thick field oxide. The anode of the device structure is a silicon wafer directly bonded to the field oxide.

The optical-beam-induced currents (OBIC) method and its application to high-voltage planar junctions will be introduced. Measurements are performed on a p+-n diode with a cylindrical junction edge. These measurements illustrate the response of the OBIC signal when negative or positive surface charges are present. It will be shown that multiple field ring structures, which are difficult to optimize, can be improved by combining OBIC measurements with Brieger's model. A fieldring structure with four rings is optimized to block 1550 V on a 9 × 1013n-substrate. In a reverse-biased planar junction the point of maximum carrier multiplication is found to be some micrometers below the surface (depending on the junction depth). We used the wavelength dependence of the OBIC signal to show that a variation of lateral doping (VLD) structure with 20-µm junction depth breaks down between 5 and 10 µm below the surface.

In this brief a new concept for high-voltage planar junctions is presented. The necessary widening of the space-charge region at the junction surface is obtained by implantation through small openings in the oxide mask and subsequent drive-in, leading to a controlled smeared-out dopant distribution. Compared to other planar junctions, this concept also yields a gain in active chip area. Experimental results show the validity of the concept.

The stability of thin interfacial oxide layers between bonded silicon wafers is investigated experimentally and theoretically. For usual bonding temperatures around 1100 °C and typical times of a few hours, the oxygen diffusivity is not high enough to allow the oxide layer dissolution. For aligned wafers of the same orientation, the oxide layer instead tends to disintegrate in order to minimize the SiO2/Si interface energy. It is possible to stabilize a uniform interfacial oxide layer by rotationally misorienting the two wafers by an angle θ exceeding a critical angle, θ crit, estimated to be between 1° and 5°.

A technology is presented that will allow the fabrication of thin III-V compound semiconductor layers of low dislocation density on silicon substrates. GaAs and InP wafers were successfully bonded to bare and oxidized silicon substrates in an experimental setup that produces a microcleanroom for bubble-free bonding in any environment. The bonding strength was found to be comparable to that of Si on oxidized Si and sufficient to subsequent grinding and polishing of the bonded wafers.

The bonding speed (or contact wave velocity) of silicon and fused quartz wafers has been measured as a function of temperature. The results show that the bonding process stops to operate at temperatures above 90°C and 320°C for fused quartz and bare silicon wafers, respectively. By comparing our results to infrared spectra obtained from silica gel we develop a tentative model of the bonding process. This model is based on the assumption that the initial wafer bonding process occurs via hydrogen bonds of adsorbed water. This model explains why the bonding strength increases in two distinct steps during high temperature annealing. By introducing a phenomenological time constant τ we can also account for the fact that in an intermediate temperature range the bonding strength does not depend on annealing time as it has been reported in the literature.

Tunneling diodes with highly doped and abrupt pn-junctions, and p+nn+ diodes were fabricated by bonding 4 inch silicon wafers at room temperature. After low temperature annealing (300–800°C) the electrical properties of the bonding interface could be changed by applying high currents up to 500 A/cm2. For tunneling diodes stressed with high current densities negative resistance effects have been obtained. The p+nn+ diodes with bonded n+ and p+ emitters showed S-shaped current switching observed in p-n-I-M structures. It is shown that due to the presence of an oxide at the bonding interface the current is limited in bonded pn-junctions.