24 results on '"Regnier, Arnaud"'
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2. EEPROM endurance degradation at different temperatures: State of the art TCAD simulation
3. Morphology and reliability aspects of 40 nm eSTM™ architecture
4. A novel test structure with two active areas for eNVM reliability studies
5. 40nm SONOS Embedded Select in Trench Memory
6. Performance Trade-Off of RFSOI Switches Under Scaled Bias Conditions
7. Experimental setup for non-destructive measurement of tunneling currents in semiconductor devices
8. A Schmitt trigger to benchmark the performance of a new zero-cost transistor
9. Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor
10. SuperCAST: a full free addressable memory array
11. Simulation of state of the art EEPROM programming window closure during endurance degradation
12. Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology
13. Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology
14. Hot Electron Source Side Injection Comprehension in 40nm eSTM™
15. Notched Gate and Graded Gate Oxide Processing for Reduced Capacitance Application in RF MOSFETs.
16. TCAD investigation of zero-cost high voltage transistor architectures for logic memory circuits
17. Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array
18. A new flash architecture for embedded low energy applications: ATW (Asymmetrical Tunnel Window)
19. Optimization of the ATW Non-Volatile Memory for Connected Smart Objects
20. Modeling Halo Implant Failures in MOS Sub-Micron Technology
21. Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology
22. Non volatile memory reliability prediction based on oxide defect generation rate during stress and retention tests
23. A Dual-Gate Memory Cell with Two Inter-Poly Oxides
24. Quantum effects influence on thin silicon film capacitor-less DRAM performance
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