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In the era of Internet of Things (IoT), an increasing amount of sensors is being integrated into intelligent wearable devices. These sensors have the potential to produce a large quantity of physiological data streams to be analyzed in order to produce meaningful and actionable information. An important part of this processing is usually located in the device itself and takes the form of embedded algorithms which are executed into the onboard microcontroller (MCU). As data processing algorithms have become more complex due to, in part, the disruption of machine learning, they are taking an increasing part of MCU time becoming one of the main driving factors in the energy budget of the overall embedded system. We propose to integrate such algorithms into dedicated low-power circuits making the power consumption of the processing part negligible to the overall system. We provide the results of several implementations of a pre-trained physical activity classifier used in smartwatches and wristbands. The algorithm combines signal processing for feature extraction and machine learning in the form of decision trees for physical activity classification. We show how an in-silicon implementation decreases up to 0.1 µW the power consumption compared to 73 µW on a general-purpose ARM's Cortex-M0 MCU.

Smart vision-based IoT applications operate on a sub-mW power budget while requiring power-hungry always-on image processing capabilities. This work presents a system-on-chip (SoC) that enables hierarchical processing of face analysis under multiple sub-mW operating scenarios using two tightly coupled machine learning (ML) accelerators. A dynamically scalable binary decision tree (BDT) engine for face detection (FD) allows triggering a multi-precision convolutional neural network (CNN) engine for subsequent face recognition (FR). The 22nm SoC can therefore dynamically trade-off image analysis depth, frames-per-second (FPS), accuracy, and power consumption. It implements complete end-to-end edge processing, enabling always-on FD and FR within the tight 1mW power budget of a 55mm diameter indoor solar panel. The SoC achieves >2x improvement in energy efficiency at iso-accuracy and iso-FPS over state-of-the-art (SoA) systems.

This paper presents a single-chip pulse generator developed for Ultra Wide Band (UWB) wireless communication systems based on impulse radio technology. The chip has been integrated in a CMOS 130-nm technology with a single supply voltage of 1.2 V. The basic concept is to combine different delayed edges in order to form a very short duration "logical" pulse, and then filter it, so as to obtain an UWB pulse. It is possible to vary the output pulse shape, and thus the corresponding spectrum, just by acting on the delayed edge combination. Furthermore, the pulse generator supports both position modulation (2-PPM) and polarity modulation (BPSK modulation) in order to convey data through the air. Its power consumption remains less than 10 mW for a raw data rate of up to 160 Mb/s. Spectral and temporal measurements of the single-chip pulse generator are presented with an illustration of the modulation effects on the power spectral density (PSD)

This paper describes the integration in a CMOS 130 nm technology of an ultra wide band (UWB) pulse generator. The implemented generator controls the output pulse shape, and thus the corresponding spectrum. Furthermore, the pulse generator supports both position modulation (2-PPM) and polarity modulation (BPSK) and draws 5 mA from 1.2 V. Spectral and temporal laboratory measurements of the single-chip pulse generator are presented.