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In order to use mechanism model analysis instead of experimental test to control and adjust the temperature and oven temperature curve of each part of the integrated circuit board reflow oven to make it meet the process requirements, a fitting algorithm was used to establish a heat transfer model of the reflow soldering. The established reflow soldering heat transfer model was used to simulate and fit to obtain the integrated circuit board reflow soldering oven temperature curve, and compared it with the reflow soldering experiment curve to verify the reliability of the model’s simulation performance. The comparison results show that the reflow soldering oven temperature simulation curve is in good agreement with the experimental curve, and it can replace the experimental test to find the best. On this basis, the genetic algorithm was further used to optimize the temperature setting and oven temperature curve for integrated circuit boards. After optimization, the conveyor belt velocity of the integrated circuit board is preferably 1.4799cm/s, and the set temperature of temperature zones is 179 °C at small temperature zones 1~5, 185 °C at small temperature zone 6, 235 °C at small temperature zone 7, and 264 °C at small temperature zones 8~9; the area of the oven temperature curve that exceeds 217 °C decreases by $831.1611~^{\circ }\textrm {C}\cdot \text{s}$ , and its symmetry with respect to the peak is better, which is much closer to the ideal oven temperature curve. The research results provide a useful reference for the design of integrated circuit board reflow soldering process.

This paper present the preliminary results regarding the application of a simple bang-bang control strategy to a custom-made SMD reflow oven. This appliance was built by retrofitting a recycled electric oven where both measurement and actuation chains are included. It will be shown that set-point tracking cannot be attained accurately and that severe temperature oscillations are observed. info:eu-repo/semantics/publishedVersion

Current and next-generation high power devices require a new set of materials with higher electrical and thermal conductivity to efficiently spread and remove increased waste heat. Kuprion's ActiveCopper technology enables the formation of bulk copper joints at typical soldering temperatures, yet the resulting interconnects are stable up to 500°C or more. This technology has been developed for a number of applications including die attach, thermal vias, and a replacement for WCu heat spreaders. Die attach materials can be dispensed, screened, or stenciled like traditional solder pastes followed by a solder-like thermal profile in a reflow oven under an inert atmosphere. Sintering can be achieved with or without pressure. Thermal vias are generated by stenciling an ActiveCopper paste directly into open circuit board cavities up to 4 mm in diameter followed by hot pressing under conditions similar to those used for traditional PCB manufacture. The resulting copper vias have thermal conductivity up to 330 W/mK, are solder compatible with or without further surface finish, and show excellent bonding to electroplated copper on the via sidewalls. Near net shape heat spreaders akin to WCu or AlSiC can also be generated via hot pressing or injection molding. The CTE of vias and spreaders can be tuned by adjusting the formulation of the original paste. ActiveCopper technology enables the design of all-Copper systems that can handle the increased thermal demands of next-generation electronics while avoiding failure modes attributed to intermetallic formation. Copper also presents an advantage over silver-based systems which show increased migration, dendritic growth, and voiding under higher thermal and electrical loads.

Uneven temperature distribution poses a big challenge on reflow soldering of surface mount components. Particularly, when components with different thermal mass are mounted on a large size of PCB, temperature gradient across the board can cause various assembly defects. Formation of a robust solder joint is closely associated with solder temperature profile which is hard to be measured experimentally. numerical simulation is an effective method to predict the solder joint temperatures which can be used as a reference to optimize the reflow profile.In this study, CFD modeling was developed to simulate solder joint temperature profile in reflow process. The profile is not a single line, but a band or process window. to achieve a good soldering quality, the non-uniformity of the solder temperatures should be within the recommended temperature profile band. The optimized thermal profiles and corresponding temperature setting of reflow oven can contribute to actual experiment and production.

This study demonstrates laser assisted bonding (LAB) of SMD Tantal Elko and MLCC (Multilayer Ceramic Chip Capacitor) capacitors and presents a comparison to conventional bonding using solder paste and reflow oven. The LAB technique, unique to Pac Tech, has greatly improved ensuing properties of packages over conventional oven reflow processes. As the LAB process is temperature controlled, it allows for a non-destructive yet fast and minimally invasive reflow of the bond-layer (solder). While the LAB process was demonstrated previously in terms of a wide range of applications, its feasibility and advantages have not yet been assessed for the stacking of passive SMD elements such as capacitors or resistors [1]–[3] and [4]. In this study, the 3D stacking possibilities of SMD capacitors will be evaluated. This technique allows the vertical or horizontal arrangement of the SMD elements on top of each other. The overall footprint of a given device such as a capacitor can be reduced, as it can be replaced by a stack of two or more smaller devices. To evaluate the potential of the LAB process, several sizes of SMD capacitors (3216M, 2012M and 1005M) were bonded and stacked. A parametric study was performed to evaluate suitable process windows for a given number of samples. To analyze test assemblies, several techniques were employed such as microscopic inspection, electrical qualification, 3D surface scans, shear-test and cross-sectional analysis. The robustness of the assemblies was investigated via a vibration test. Specifically, the mechanical properties of the devices were simulated through several cycles of high frequency vibration tests relative to three-dimensional loads. Finally, future perspectives regarding potential applications of passive SMD element stacking and LAB SMD assembly are elucidated.

After the introduction of lead free solder in the packaging industry, there has been ongoing research to find solder alloys that have a low melting point. Boards having solders that reflow at a lower temperature would not only reduce the overall operating cost but also reduce board warpages and reduce damages to sensitive components. The most common low temperature solder is the eutectic tin-bismuth solder with a composition of 42Sn-58Bi. For this study, cylindrical samples of eutectic solder were reflowed in a reflow oven. The reflowed specimens were then subjected to isothermal uniaxial tensile tests at temperatures of 25, 50, 75, and 100 °C at strain rates of 10-3, 10-4, and 10-5 sec-1. The results from the tensile tests were then used to predict the nine Anand Parameter Coefficients. The Anand model is widely used to predict the stress-strain characteristics of viscoplastic materials and is incorporated in commercial finite element software such as ANSYS. The Anand predicted curves were then compared with the experimental tensile curves to determine the model’s ability to accurately predict the stress-strain behavior at any particular strain rate and test temperature. Finally, the obtained Anand Parameters were used to predict the reliability of a BGA package had it been made of SAC305 solder balls and eutectic solder paste.

During the experiment, pressure-less silver sintering pastes that can sinter using a conventional reflow oven for die-attach applications were developed. This development makes it possible to produce die-attach assemblies in a continuous and high throughput fashion for mass production. Different reflow profiles such as “ramp-up and peak” and “ramp-up and plateau” types were tested and high shear strength joints with no voids were obtained. For each sample, the sintering time was around twelve minutes or less, which is about one order of the magnitude that is presently used for box oven sintering time. Two sintering pastes, A and B, were developed. Paste A has been used to study the relationship between processing conditions (reflow oven sintering temperature and atmosphere such as air vs nitrogen) and the die-attach structures (with varied substrate materials such as copper or active metal brazing (AMB) and surface metallization such as copper, silver, or gold). Under the same combined conditions of sintering temperature, atmosphere, and substrate type, the Ag metalized substrate gave the strongest joint shear strength. In comparison, Au metalized substrate displayed the weakest strength because of the formation of a “depletion layer” as a result of the diffusion of silver on gold surface, leaving behind a weak connection between sintered silver and Ag-Au layer. For the above noble metal metallized surfaces, sintering in air normally results in stronger joint shear strength than that in a nitrogen atmosphere. On the bare Cu metallized surface with nitrogen sintering, increasing the sintering temperature and changing to paste B are two ways to increase joint shear strength. Sintering on an AMB substrate displays around 10Mpa higher shear strength than that on a Cu substrate, indicating the importance of surface morphology. When sintering at 250°C in air, oxygen can help accelerate the inter-diffusion between Cu substrate and sintered Ag and enhance interfacial adhesion, increasing the shear strength. A higher sintering temperature reduces the adhesion due to the formation of large amounts of copper oxide; therefore, control of the optimum temperature range is key to obtaining a strong joint in air.

Screen printing is the most common method used for the production of printed electronics. Formulating copper (Cu) inks that yield conductive fine features with oxidation and mechanical robustness on low-temperature substrates will open up opportunities to fabricate cost-effective devices. We have formulated a screen-printable Cu metal-organic decomposition (MOD) ink comprising Cu formate coordinated to 3-(diethylamino)-1,2-propanediol, a fractional amount of Cu nanoparticles (CuNPs), and a binder. This simple formulation enables ∼70–550 μm trace widths with excellent electrical [∼8–15 mΩ/□/mil or 20–38 μΩ·cm] and mechanical properties with submicron-thick traces obtained by intense pulse light (IPL) sintering on Kapton and poly(ethylene terephthalate) (PET) substrates. These traces are mechanically robust to flexing and creasing where less than 10% change in resistance is observed on Kapton and ∼20% change is observed on PET. Solderable Cu traces were obtained only with the combination of the Cu MOD precursor, CuNP, and polymer binder. Both thermally and IPL sintered traces showed shelf stability (

Purpose The presence of voids in the solder layer has been considered as one of the main issues causing reliability problems in optoelectronic devices. Voids can be created due to trapped gas, clean-up agent residues (fluxes), poor wettability at interface or shortcoming of the reflow process. The voids hinder the heat conduction path and subsequently, the thermal resistance will increase. The purpose of this paper is to investigate the influence of lead-free water-washable Sn96.5Ag3.0Cu0.5 (SAC305) solder paste (SP) voids on the thermal and optical performance of white high-power (HP) surface-mounted device (SMD) light-emitting diode (LED). Design/methodology/approach Five LEDs are mounted on five SinkPAD substrates by using the SP. The SMT stencil printing is used to control the thickness of the SP and reflow oven for the soldering process. The fraction of voids in the SP layer is calculated using the X-ray machine software. The thermal parameters of the LEDs with different voids fraction and configuration are measured using a thermal transient tester (T3Ster) system. In addition, the optical characterizations of the LEDs are determined by the thermal and radiometric characterization of power LEDs (TeraLED) and the electroluminescence by using the spectrometer. Findings The results showed that the thermal performance and temperature distribution are improved for the LED with lower voids fraction and good filling state of soldering. In addition, luminous flux, efficacy and color shift of the LEDs with different fraction and configurations of voids on the SP layer are compared and discussed. It is found that the color shift of LED1 of low voids fraction and higher thickness are less than other LEDs. Originality/value The paper provides valuable information about the effect of water-washable SAC305 SP voids fraction and filling state of solder on the thermal and optical performance of ThinGaN HP SMD LED. A comprehensive overview of the outcomes is not available in the literature. It was shown experimentally that the voids fraction, height and configuration of the SP layer could strongly influence the heat dissipation efficiency and thermal resistance. This study can help in heat diffusion investigation and failure analysis of HP SMD LEDs.

In this paper, the vacuum reflow soldering technology for semiconductor laser chips in optoelectronic devices was studied and analyzed in a systematic manner. Through the study on the key elements in the reflow soldering process, such as the selection of solders, chamber vacuum, flux, and the pressure applied by the fixture on the chip, this paper focused on exploring the formation mechanism of voids in the solder layer when the device was resoldered. Also, the change in the movement of gas bubbles in the voids with changing reflow oven chamber conditions and its underlying law were analyzed, by preparing 200 C-package semiconductor laser diodes and verifying the reliability and stability of the theoretical analysis through inspection and test aging. which could provide a theoretical basis for the use of the vacuum reflow soldering technology to reduce the void rate in the soldering process of devices.

In the competition to excel in the Industrial 4.0 race, companies especially in Semiconductor Industry, strive to attain efficiency by removing process bottlenecks, improving productivity and increasing machine availability during operation. As so, this research was conducted to analyze the machine’s availability based on various preventive maintenance (PM) scheduling. A model was developed in WITNESS 14 Manufacturing Performance Edition software to imitate the Surface-mount Technology (SMT) line in a manufacturing system. The model was build based on a serial layout of five machines which are a screen printer, glue dispenser, chip shooter, pick and place and reflow oven. Then, the simulation was run to study the availability of each machine with relation to different stoppages intervals and duration based on the selected PM schedule. The findings of this project show that PM for an SMT line should be carried out every week with 30 minutes PM duration to achieve high machine availability and minimal machine downtime.

In this research, the microstructure evolution of Sn-Cu based solder paste on the electroless nickel immersion gold substrate was investigated. The aims are to study the microstructure formation of as-reflowed Sn-10 wt.% Cu paste on the substrate. Besides, the evolution of the interfacial intermetallic compound layer and bulk solder microstructure of the solder joint that subjected to multiple reflowed were also investigated in this paper. The Sn-0.7 wt. % Cu solder paste was mixed with copper powder to produce the Sn-10 wt. % Cu solder paste. The mixed solder paste then reflowed on the electroless nickel immersion gold surface finish substrate to form a solder joint in a reflow oven. Then, the as-reflowed solder joint was undergo multiple reflowed processes until the sixth time. It was noted that multiple reflowed process influenced the microstructure evolution of Sn-0.7 wt. % Cu and Sn-10 wt. % Cu solder samples on electroless nickel immersion gold substrate. The Cu6Sn5 IMC in the bulk solder microstructure for both solder samples become coarsen after 6th times reflowed cycles. Meanwhile, the primary Cu3Sn phase in Sn-10 wt. % Cu solder paste was found to dissolve. The morphology of the needle-shaped interfacial intermetallic compound layer was changed to layer-shape and the intermetallic compound thickness of both solder joints on electroless nickel immersion gold substrate was increased with the number of the reflow process cycles. The grain size and thickness of IMC formation for both solder joints are directly proportional to the multiple reflow cycles.

This essay focuses on the temperature variation law of the center of the target board soldering area at a certain position when the reflow oven starts working as the core discussion. Using the principle of heat conduction, Fourier's law to solve the problem of temperature values and temperature change laws in the center of the soldering area of the target circuit board at different locations under set conditions. As in the actual process, the temperature change in the center of the soldering area is limited to certain conditions, we can use the target planning, prediction methods, to build a model to solve the maximum problem. At the same time we need to consider the quality of the target circuit board, the use of neural networks, genetic algorithms to establish optimization models for target optimization, and ultimately the optimal furnace temperature curve.

This chapter aims to produce the results for reliability and availability for a two identical unit cold standby PCB manufacturing system consisting of three subsystems: Stencil Printer (PT), Pick and Place (P&P), Reflow Oven (RO). It is considered that the operative unit may fail due to different kinds of faults in its subsystems, and when it fails the standby unit is switched in so that system remains operative or in production mode. State transition diagram has been constructed and various recursive relations have been written. The availability and reliability analysis of the unit is carried out using the SMP (Semi-Markov Process) and RT (Regenerative Techniques), taking into account the failure and the repair rates of its subsystems. Various conclusions regarding the reliability and availability have been evaluated numerically and interpreted graphically in steady state.

The line balance rate (LB%) has been extensively used in the production on assembly lines and is often considered a performance index. The higher LB%, the shorter the wait between stations. For SMT process, however, a mounter is more expensive than others, such as solder printer, solder paste inspector and reflow oven. For this, a modification of equation is proposed in this study to incorporate a machine other than a mounter in the equation when it becomes a bottleneck, thus approaching more practical applications.However, high LB% is not necessarily equal to high production because the equation has its own limits. Original LB% formula cannot show whether the production line has slowed down. For this, it is proposed in this study to combine the values claimed by vendor and the percentage of actual production achieved through CPH (components per hour) as a supplement for LB%. After being actually applied to the SMT production line, CPH% can provide managers and engineers with information on production output.

Ag sintering has been paid considerable attention to an alternative to soldering in die attach for decades, especially for high power electronics packaging because of its high melting temperature (962°C), highly thermal and electrical conductivity of the sintered silver joints, and low process temperature that is normally less than 275°C. Ag sintering reported in literature and currently used in industry, however, is long time process, especially for pressureless sintering process, which would takes an hour at sintering temperature in air so as to achieve strong bonding. Though air is good for organic capping agents to be burnt out during sintering process, it would cause the oxidation of air-sensitive components in power electronic package during assembly. We recently developed a series of silver sinter pastes that can fast sinter at the peak temperature range from 240°C to 275°C, with a shortest sintering time of 2min, in nitrogen using a conventional reflow oven like BTU oven, to form strong sintered Ag joints on Ag and bare Cu DBC substrate, and/or bare Cu coupon with Ag Si or bare Cu dies. In the present paper we will present silver sintering process conditions, shear strength, microstructure of the sintered Ag joints, and preliminary reliability tests. Thermal shock test with a profile of -55 to 155°C, 10min of dwell time was employed to evaluate thermomechanical reliability of the sintered Ag joints bonding Ag Si die on bare Cu DBC substrate made in air and nitrogen by BTU reflow oven. Scanning electronics microscopy (SEM) was utilized to characterize cross-section microstructure of the sintered Ag joints. Influence of sintering process conditions on shear strength and cross-section microstructure of the sintered Ag has been investigated extensively.

Industry 4.0 guidelines drive technology advancement, also the improvement of safety and comfort in the workplace environment. The factories utilizing surface mount technology lines have well-established setups, driven by the good practice of the last decades. However, the digitalization and connected nature of the used apparatus enable new opportunities from the human-machine interface (HMI) and occupational safety and health (OSH) aspects as well. Our paper focuses on a case, where a reflow oven is extended with a novel Grid-Eye sensor (8x8 IR-based temperature sensor IC). The applied component enables contactless investigation of the bulk and surrounding of the reflow oven, monitoring the cooling printed circuit board assembly on the PCB holder, even detecting the intrusion of a colder surface (e.g. the hand of a human operator). The case is tested on a bench-top IR oven, but the presented method could be applied to inline convection-based ovens as well.

Surface Mount Technology (SMT) is a widely used manufacturing technology especially in semiconductor and electronics industries. This paper demonstrates host-equipment communication by adopting the Semiconductor Equipment Communication Standard and Generic Equipment Model (SECS/GEM) protocol, which is maintained by Semiconductor Equipment and Materials International (SEMI). This communication standard has been adopted worldwide as it enables manufacturers to collect, monitor and control equipment from a remote distance. In this work, we develop an application written in C# language on Window Forms Application platform, setting up SECS/GEM communication to collect and monitor alarm status, temperature and number of PCBs under processed from a reflow oven used in a SMT manufacturing plant.

A susceptor-assisted microwave (SAM) has been recognized as one of soldering methods for lead-free solder alloys. In this study, the effect of the soldering method on the wettability, microstructure, and tensile properties of the Sn3.0Ag0.5Cu (SAC305) solder alloy were investigated. The SAC305/Cu was reflowed using a conventional reflow oven (SAC305-O) and a SAM (SAC305-H40) heating. The wettability was measured by the wetting angle and the spreading ratio. The morphology and composition of the intermetallic compound (IMC) joint were evaluated on top-surface and cross-sectional views. The ultimate tensile strength (UTS) was characterized at a maximum load of 5 kN and a crosshead speed of 1 mm min−1. The results indicated that wetting angle and spreading ratio for SAC305-O (30.94°, 86.63%) and SAC305-H40 (18.60°, 92.20%) had a sufficient requirement on the wettability. The top-surface (round shape) and cross-sectional (scallop-shaped) morphologies of SAC305–H40 exhibited smaller grain sizes and thinner (2.47 µm) IMC layers at the solder joint compared to those of SAC305–O (3.65 µm). Compositional analysis confirmed that the observed IMCs consist of Cu6Sn5, Ag3Sn, and Cu3Sn for both samples. The UTS of SAC305-H40 (43.75 MPa) was greater than that of SAC305-O (31.30 MPa). The SAC305-H40 had a 28% reduction in the IMC layer thickness and a 29% increase in the UTS compared to that of SAC305-O. From the findings, the SAM method had a remarkable performance and had a potential as a replacement for the conventional method.

Sintered-silver is a candidate material to supplant solders for interconnects in power electronic packaging for many reasons including its desirably high electrical and thermal conductivities and compliance to Restriction of Hazardous Substances (RoHS) guidelines. The shear failure stress of interconnects though is limited by whatever constituent is the weakest, and that includes any employed plating. In the present study, silver-platings were processed electrolytically, electrolessly, and through sputter deposition and their influence on the entire “interconnect system” shear strength was examined. Test sets employing gold plating and no plating were included for comparison and to aid interpretation. Ambient-air, reflow-oven-processed, pressureless-sintered-silver interconnects were identically fabricated with all plating test sets. It was found that all considered silver-plating methods produced consistently strong (characteristic failure stresses > 55 MPa) sintered-silver interconnects. Because failures tended to be adhesive in all six sets, differences in failure stress among the silver-plated sets and the gold-plated or unplated sets were likely due to differences in the adhesive strength of the sintered silver with silver-plating, gold-plating, or direct bonding with copper.

A method was developed to pressurelessly fabricate strong and consistent sinterable-silver joints or interconnects using reflow oven heating. Circular sinterable-silver interconnects, having nominal diameter of 5 mm and 0.1 mm thickness were stencil printed, contact-dried, and then pressurelessly sinter-bonded to Au-plated direct copper bonded ceramic substrates at 250 °C in ambient air. That sintering was done in either a reflow oven or a convective oven (latter being a conventional heating source for processing sinterable-silver). Consistently strong (>40 MPa) interconnects were produced with reflow oven heating and were as strong as those produced with convective oven heating. This is significant because reflow oven technology affords better potential for continuous mass production and it was shown that strong sintered-silver bonds can indeed be achieved with its use.

Purpose The purpose of this paper is to increase the reliability of manufactured electronics and to reveal reliability significant factors. The experiments were focused especially on the influence of the reflow oven parameters presented by a heating factor. Design/methodology/approach The shear strength of the surface mount device (SMD) resistors and their joint resistance were analyzed. The resistors were assembled with two Sn/Ag/Cu-based and one Bi-based solder pastes, and the analysis was done for several values of the heating factor and before and after isothermal aging. The measurement of thickness of intermetallic compounds was conducted on the micro-sections of the solder joints. Findings The shear strength of solder joints based on the Sn/Ag/Cu-based solder alloy started to decline after the heating factor reached the value of 500 s · K, whereas the shear strength of the solder alloy based on the Bi alloy (in the measured range) always increased with an increase in the heating factor. Also, the Bi-based solder joints showed shear strength increase after isothermal aging in contrast to Sn/Ag/Cu-based solder joints, which showed shear strength decrease. Originality/value The interpretation of the results of such a comprehensive measurement leads to a better understanding of the mutual relation between reliability and other technological parameters such as solder alloy type, surface finish and parameters of the soldering process.

This paper presents the study of infrared (IR) reflow oven characteristics for suitable operating conditions of the flexible printed circuit board (FPCB) in the reflow soldering process. A computer-based model that imitates a real-time oven was developed with practical boundary conditions. Since the radiation effect is dominant in the reflow process, a discrete ordinate (DO) model was selected to simulate the effect. The experimental work acts as a benchmark and the reflow profile was set to follow the standards of JSTD-020E. The simulation of the model has a great consensus between the experimental data. It was found that the temperature distribution was inhomogeneous along with the phases. The FPCB surface also has a higher surface temperature than oven air during the operating reflow profile. An in-depth study using the simulation approach reveals that the temperature distribution of the desktop reflow oven is dependent on several factors, namely fan speed, FPCB position, and FPCB thickness. The rotational fan generates an unsteady flow that induces inhomogeneous temperature at different positions in the reflow oven cavity. The results are useful for studying further improvements to achieve temperature uniformity within the oven chamber.

The paper presents an analysis of measuring and evaluating heat transfer coefficients for Vapour Phase Soldering (VPS) in saturated vapour for electronics assembling. The prepared Printed Circuit Board (PCB) is practically considered as a horizontal plate (rectangular or disc shaped) during the process. The novel measurement setup is optimized to minimize any perturbing effect of the instrumentation. The obtained temperature data is processed to calculate the heat transfer coefficient distribution on the boards, where the inhomogeneity of the heating is presented according to the geometry of the PCB. The differences reveal the need of careful circuit and component placement design, while the heat transfer coefficient values may considerably differ even on a simple board shape and surface during heating according to the central parts and edges-corners of the rectangular board. The effect is more emphasized on rectangle boards, however edge effect it is also observable on disc shaped boards as well. The paper also points to related design and manufacturing recommendations.

Purpose The purpose of this paper is to evaluate selected methods of reduction voidings in lead-free solder joints underneath thermal pads of light-emitting diodes (LEDs), using X-ray inspection and Six Sigma methodology. Design/methodology/approach On the basis of cause and effect diagram for solder voiding, the potential causes of voids and influence of process variables on void formation were found. Three process variables were chosen: the type of reflow soldering, vacuum incorporation and the type of solder paste. Samples of LEDs were mounted with convection and vapour phase reflow soldering. Vacuum was incorporated into vapour phase soldering. Two types of solder pastes OM338PT and LFS-216LT were used. Algorithm incorporated into X-ray inspection system enabled to calculate the statistical distribution of LED thermal pad coverage and to find the process capability index (Cpk) of applied soldering techniques. Findings The evaluation of selected soldering processes of LEDs in respect of their thermal pad coverage and statistical Cpk indices is presented. Vapour-phase soldering with vacuum is capable (Cpk > 1) for OM338PT and LFS-216LT paste. Convection reflow without vacuum with LFS-216LT paste is also capable (Cpk = 1.1). Other technological soldering processes require improvements. Vacuum improves radically the capability of a reflow soldering for an LED assembly. When vacuum is not accessible, some improvement of capability to a lower extent is possible by an application of void-free solder pastes. Originality/value Six Sigma statistical methodology combined with X-ray diagnosis was used to check whether applied methods of void reduction underneath LED thermal pads are capable processes.

During solder reflow of smaller and smaller microelectronic interconnections, a robust soldering process can become challenging, resulting in opens or bridging. In this work, a customized real time resistance monitoring (RTRM) setup is developed to observe the resistance of a solder connection in real-time during reflow to better understand the challenges of soldering. Two types of solder paste are studied with RTRM. Solder A was fresh while solder B was one year old. We found solder B in general has a lower room temperature resistance before reflow than solder A. During reflow, the resistance signals behave differently between solder A and solder B. For example, in solder B, an episode of high resistance (24.40 ± 16.04 kΩ) is observed for 4–58 s not long before melting, while solder A mainly shows resistance drops in the early stage of reflow. Microscopic images and cross-sectioning studies with respect to the special events in the resistance signal show solder compacting, solder sintering, flux segregation, and final open or connection. RTRM can be a helpful tool when developing smaller solder processes for thin film substrate with miniaturized passive and active components.

In this research study, we investigated the interfacial reaction and fracture modes in BGA solder joints prepared using Co nanoparticles doped flux. Solder joints were formed in a reflow oven at 240 °C for 45s and subsequently aged at 150 °C up to 1008 h. One set of aged solder joints was used in both microstructural characterization to examine the morphology and growth of interfacial IMC layer and nano-mechanical characterization to determine the hardness and Young's modulus of different phases. Another set was experimented in ball shear test to determine the average shear strength and crack paths in different failure modes. Results showed that the growth of Cu 6 Sn 5 enhanced and that of Cu 3 Sn suppressed due to the profound stability of Cu 6 Sn 5 in the presence of Co atoms. In the case of undoped condition, the direction of crack changed from a ductile failure mode to a brittle failure mode with respect to aging time. No catastrophic brittle failure mode was observed for Co doped solder joints. The mechanisms for the better fracture behavior in Co-doped solder joints are suggested and correlated to Cu 6 Sn 5 /Cu 3 Sn interfacial reaction.

The advanced technologies for electronics production and convection based soldering technologies are growing steadily. The enhanced reflow soldering oven with an integrated hyper pneumatic module ensures a void-free solder connection, but it requires design and installation of the process parameters in the oven in order to ensure optimized heat transfer and derive the best energy efficiency performance. This paper presents a simulation model of the thermal soldering process in the over-pressure convection oven by finite element model. This model considers the effect of the complex boundary conditions during the soldering process. A set of experimental tasks were designed to investigate the variations in the temperature profiles at selected points on the surface of the demonstrator. Moreover, the heat transfer coefficient for each thermal profile has been calculated. The simulation model can be used to predict the temperature distribution for the solder materials together with the demonstrator board. The void content in the solder material was investigated by the X-Ray analysis and correlated with the thermal process in the simulation. Hence, the optimized relation between the process set-up parameters in the oven, simulated thermal behavior, and the voids fraction in solder material are studied in detail.

ln order to adjust the temperature profde of a reflow oven to a speciftc soldering task, thermocouples are placed on selected places on the printed circuit board. Since the thermocouples have a very small thermal mass and correspondingly short response times, compared to other types of temperature sensors, they are able to record the dynamic changes in temperature that occur during a reflow process. The goal is to monitor the rather rapid temperature changes of small components (e.g. CR, CC, LED) and the slower temperature changes at larger components (e.g. electrolytic capacitors, BGA). That way the temperature profde is optimised to securely solder all components within a limited total thermal load, to prevent damage of the components. ln contrast to the established methodology to adjust temperature profdes the investigation presented in this paper focuses on measuring the solder temperature during the reflow process. A laboratory reflow oven is used, which is tailored for soldering lead-free solder prototypes and offers four channels for simultaneous temperature measurements through an integrated USB port, which also enables programmable control of the reflow profdes. ln this work the temperatures of the solder are measured directly by making use of T-type thermocouples. Although having the comparative disadvantage of being less linear than their K-type counterparts, they have the advantage of being able to integrate better with solder, hence enabling a deeper study of speciftc solder temperatures, as opposed to merely the bulk component temperatures offered by K-type thermocouples.

Cu-Cu bond is a prefer solution for shrinking interconnect pitch as it offered lower interconnect resistance with no intermetallic compound risk. Major challenge in Cu-Cu bond is the formation of copper oxide and also the long thermal process. Several approaches had been proposed in the industry to overcome the challenges are diffusion bonding, ultra-sonic bonding, Cu nano-paste, use of Formic acid and argon plasma for copper surface treatment and bit grinding process to enable good Cu-Cu bond. In this paper, we explore the use of Cu nano-paste as the bonding medium between Cu bump and Cu pad. Cu nano-paste is an attractive solution for Cu-Cu bond as it deploy similar approach as conventional solder bump flip chip process. The flux used in conventional solder bump flip chip process is replaced by Cu nano-paste and the conventional reflow oven is replaced by Formic Acid Chamber. We had demonstrated good formic acid process in dealing with Cu nano-paste in terms of low resistance value and prestige copper surface.

Measuring of gas flow inside of an reflow furnace is very important issue, helping to optimize heat transfer and decrease power consumption of such machine. Nowadays we are using lead free solder alloys and optimized profiling is a must for high quality of soldering joints and as low as possible void rate. Mostly in medical and automotive branches are these technological methods very important. Our target is reliable production, it means reliable products. This is the basics for longer lifetime of electronics at all. Measuring equipment for 3D measuring of a gas flow is one of very important things to reach this target.

With an ongoing digital transformation towards industry 4.0 and the corresponding growth of collected sensor data based on cyberphysical systems, the need for automatic data analysis in industrial production lines has increased drastically. One relevant application scenario is the usage of intelligent approaches to anticipate upcoming failures for maintenance. In this paper, we present a novel approach for anomaly detection regarding predictive maintenance in an industrial data-intensive environment. In particular, we are focusing on historical sensor data from a real reflow oven that is used for soldering surface mount electronic components to printed circuit boards. The sensor data, which is provided within the scope of the EU-Project COMPOSITION (under grant no. 723145), comprises information about the heat and the power consumption of individual fans inside a reflow oven. The data set contains timeannotated sensor measurements in combination with additional process information over a period of more than seven years.

One of the most vulnerable components of electronic circuits is the solder joints. The most common technique of soldering used in electronics is the reflow soldering. During the soldering process, different issues may occur leading to the inception of some defects (tombstone effect, flux spattering, etc.). To avoid these defects, it is mandatory to follow the parameter values of the reflow process, especially temperature values. In this paper, the temperature distribution for three types of samples (two interconnected soldering pads–without solder, with solder on one pad, and with solder on both pads) during the reflow soldering process, calculated with Comsol Multiphysics software (heat transfer 3-D module) is presented. The calculated values are then compared to the ones obtained by experiments in order to verify the accuracy of the numerical model. To carry out the computations, the latent heat of melting/solidification and the variation with the temperature of the solder parameters were considered. The results show that there is a good correlation between the measured and calculated values, the differences (for all types of samples) being lower than ±3 °C.

A system in package (SiP) is a number of integrated circuits integrated into a single module. SiP can perform various functions and are often used in small systems such as mobile phones and wearable devices. The fabrication of SiP can be challenging due to their small size and high complexity. For example, during the reflow soldering process, non-uniform temperature distribution can occur, affecting the reliability of the SiP. In this study, numerical simulation is used to investigate the thermal behavior of a SiP during the reflow process and the model is validated via experimental measurements. A forced convection reflow oven was modeled using computational fluid dynamics software where the heating of the SiP assembly was performed using a conjugate heat transfer model. A complex flow field in the reflow oven was observed from the simulation results, showing a free jet region, a stagnation flow region, a wall jet region, a recirculation region, and vortices. The simulation results agreed well with experimental data. The method developed here can accurately predict the temperature distribution in a reflow oven and allow the design of temperature profiles for the reflow process that result in minimal temperature variations across the SiP assembly.

This work investigated the effects of 1.0 wt. % TiO2 particles addition into Sn-Cu-Ni solder paste to the growth of the interfacial intermetallic compound (IMC) on Cu substrate after isothermal aging. Sn-Cu-Ni solder paste with TiO2 particles were mechanically mixed to fabricate the composite solder paste. The composite solder paste then reflowed in the reflow oven to form solder joint. The reflowed samples were then isothermally aged 75, 125 and 150 ° C for 24 and 240 h. It was found that the morphology of IMCs changed from scallop-shape to a more uniform planar shape in both Sn-Cu-Ni/Cu joints and Sn-Cu-Ni-TiO2 /Cu joint. Cu6Sn5 and Cu3Sn IMC were identified and grew after prolong aging time and temperature. The IMCs thickness and scallop diameter of composite solder paste were reduced and the growth of IMCs thickness after isothermal aging become slower as compared to unreinforced Sn-Cu-Ni solder paste. It is suggested that TiO2 particles have influenced the evolution and retarded the growth of interfacial IMCs.

In this paper, heat transfer and condensate layer formation was investigated by numerical simulations on the top side of inclined printed circuit boards during vapour phase soldering. The phase change on the inclined surface and the transfer mechanisms in the condensate layer were embedded in a three-dimensional model. Steady-state and saturated vapour conditions were applied as boundary conditions in order to study the pure effect of the inclination. Due to the electronic component and circuit board structures during soldering only moderate inclination angles were studied between 0° and 10°. It was found that a moderate inclination of the printed circuit board has considerable effects on the formation of condensate layer and consequently on heat transfer. Compared to the default horizontal orientation of the board, the thickness differences of the condensate layer can be decreased with an optimised inclination of the printed circuit board. This effect homogenizes heat transfer during the process, enabling improved solder joint quality, with reduced overall soldering failure count.

Purpose The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed. Design/methodology/approach Lead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process. Findings With the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed. Practical implications This literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process. Originality/value The unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

Purpose – The paper aims to present a comparative study of various thermocouple (TC) attaching methods for the proper measurement of soldering temperature profiling during vapour phase soldering (VPS). The heat transfer process during VPS is different from common methods, while the required heat for reflow is provided by the condensation. The condensate is a flowing layer on the board, where the dynamic behaviour also affects the local conditions on the surfaces. Temperature measurements based on TCs are also affected this way; it is important to investigate the process for deeper understanding. Design/methodology/approach – Bare printed circuit boards (PCBs) were prepared for standard K-Type TCs attachment with industry standard materials: kapton polyimide tape, aluminium tape, SMD adhesive and high-temperature solder (HTS). Heating experiments were performed in a batch-type VPS oven with Galden LS240 fluid and fixed oven parameters. Findings – According to the specific attachment requirements, HTS and Alu-tape are the suggested methods for better profiling reliability and repeatability. Alu-tape is the preferred all-around method, for fast, exchangeable, cheap, reliable and repeatable profiling in a VPS oven. It was presented that the heating factor (Q?) gives more reliable comparison overview; the time period-based comparisons may be affected by the thermal inertia, while heating factor also includes temperature conditions at the given time points. Originality/value – The paper presents the reliability of the presented methods for VPS and present suggestions for the use of different TC ends and attaching materials during condensation heating of the PCBs. Also a new approach on profiling data evaluation based on the heating factor is presented and suggested for wider use.