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In the digital world, all the transmitted data is vulnerable and prone to attack. To reduce the vulnerability, security is needed for the data. The security of the data can be enhanced by implementing cryptographic techniques. Thus, the sender and the receiver can only view the data by implementing cryptography, whereas a third party cannot intervene. Cryptographic algorithms are used in the IoT, online banking, Web servers, etc. The Advanced Encryption Standard (AES) is symmetric-key cryptography; it has the same key for both the encryption and decryption process. Each step in the AES algorithm is modified by using the key generated for each round, so each step of the AES is made key-dependent. This gives the dynamic AES algorithm. However, the delay and area are comparatively higher than the traditional method. Thus, the proposed method involves combining two steps, the sub-byte transformation and shifting rows. By doing this, the registers used to store the sub-byte data are removed. Thus, eliminating registers leads to less area consumption. Simulation is done using Verilog HDL in ModelSim and the synthesis is done in Xilinx Design Suite.