Search

Carbohydrate (CHO) loading is believed to be an ergogenic dietary asset for aerobic performance by maximizing CHO oxidation and to combat glycogen depletion within the working muscle cells. However, evidence-based research has displayed that an increase in fat metabolism, subsequently lower CHO oxidation, may provide sufficient energy during submaximal and maximal exertion through beta oxidation.​​For this reason, active volunteers were recruited to undergo a double-blind study to determine if an acute carbohydrate loading dietary supplement was effective in enhancing performance on a maximal oxygen uptake (VO2) test.​​Eleven college aged (22.09​±1.3) students ​(male n=8, female n=3) participated in this double-blind randomized study. Subjects consumed either a CHO (1g/kg body weight) or placebo supplement followed by a 12 hour fast. Following this fast, first testing session consisted of a seven-point skin caliper for body composition (% body fat), fasting blood glucose as measured by point of care finger stick method using Abbott Precision blood glucose meter (mg/dL), and a VO2 max test (mL/kg/min) measured by a modified Tread Sport Treadmill Protocol. Prior to the second test date, the subject consumed either CHO supplement or placebo, followed by 12 hour fast. Second test day consisted of fasting blood glucose, and VO2​ max test. Protocols were matched for the second bout of testing.​​A paired samples t-test (SPSS v.26) was conducted to determine significance (​p≤0.05​) on each of the four variables: VO2 max, fasting blood glucose (GLU), anaerobic threshold (AT), and respiratory quotient (RQ). No significant differences were found when comparing groups on all variables (VO2 ​p=0.923​,GLU ​p​=0.099​,AT ​p=0.641, ​RQ ​p=0.372​).​​ Acute CHO loading has no significant impact on performance variables as defined by AT, RQ, and VO2 max.

In this paper, significant improvement in cascode LNA performance is demonstrated by using a new high self gain (HSG) common gate (CG) transistor. Emphasis has been on making the output conductance $g_{ds}$ lower and flatter with drain bias. A prototype cascode LNA is designed and fabricated using the developed HSG device in state-of-the-art 0.13 RF SOI technology. Thanks to the HSG device, more than +5 dBm input inter-modulation product (IIP3) improvement is seen in measurements. Very high gain of 19.5 dB at 2.5 GHz with IIP3 value of +1.5 dBm are seen in measurements. Due to optimized transistor sizing, the designed LNA operates at low power of 6.25 mW where 5.2 mA of current is drawn from 1.2 V supply. With integrated high quality factor inductors on high resistivity SOI substrate, the LNA also demonstrates very low noise figure of 0.85 dB. Furthermore, excellent correlation between model simulations and measurements is demonstrated.

A 6 GHz CMOS low-noise amplifier (LNA) with very low noise-figure (NF) of 0.92 dB is reported in this paper. An inductively degenerated cascode topology is used for the LNA. The common source device is a floating body transistor for higher unity gain cut-off frequency and lower NFmin while the common gate device is a body contacted device with higher self gain. High resistivity (HR) silicon-on-insulator (SOI) technology renders higher quality factor (Q) values for inductors which results in reduced NF. The prototype LNA is fabricated (Fig. 1) and characterized using a 180 nm RF-SOI CMOS technology. Measurements show 15.9 dB of gain, 0.92 dB of NF, -1.1 dBm of input third-order intercept point (IIP3) for the LNA, with 12 mW dc power consumption.

Over the last few decades, SiGe BiCMOS has survived the continued onslaught of RF-CMOS technologies. SiGe HBT invented in late 1980's and later introduced as a BiCMOS technology served as a sweet spot in the emerging RF market, thanks to the SiGe HBT's higher power and better noise characteristics. It did not take very long for RFCMOS scaling roadmap to catch up to SiGe HBT performance levels and displace it from high-volume market segment like RF cellular transceivers. Now with the advent of 5G millimeter-wave (mmWave) applications demanding higher power and lower noise for the front-end, will SiGe BiCMOS once again come back to the forefront to address this market? In this paper we will take a closer look at some of the key aspects of a 130 / 90nm SiGe BiCMOS relative to a 28nm bulk RFCMOS technology for addressing mmWave front-end as well as potential opportunities that lie ahead with scaling.

In this paper, we first analyze an LNA core, cascode structure cut off frequency and power gain relationship with device parameters. Then we discuss the LNA design differences between FET LNA and SiGe LNA during design optimization. SOI floating body FETs have advantages in higher Ft in the optimized current biased region and can offer more design flexibility, while SiGe NPNs need much less trade off room. With this design methodology, we design 5GHz LNAs based on 120nm SOI FET and 0.12um SiGe NPN with 5mA current limitation. The SOI NFET LNA achieves 16dB gain and 1.2dB NF, while SiGe achieves 20dB gain and

In this paper, we present 2.4/5.5 GHz LNAs with SPDT Switch for WiFi Front-End Modulate Integrated Circuit (FEM IC) based on high resistivity substrate 0.35um SiGe BiCMOS process. For the 2.4GHz LNA, the bias circuit's effect on the nonlinearity is analyzed and measured, and then a new bias circuit is proposed. With 2.7V supply, it consumes 4.2mA current. The measured Gain is about 14.6dB with input and output return loss better than −10dB. The Noise Figure (NF) is 1.16dB, output 1dB compression point is ∼8dBm, and OIP3 is about 20dBm. For the 5.5GHz LNA with proposed new bias circuit and SPDT switch operating at 7.3mA current with 2.7V power supply, 2.1dB NF and 19dBm OIP3 are achieved in the post layout simulation.