Hardware Security is a key issue with the emergence and proliferation of embedded systems. Many embedded systems like smart cards, RF-id tags, mobile phones and PDAs run cryptographic algorithms running on dedicated cryptographic ICs to perform operations like secure identification, authentication and communication. Even though cryptographic algorithms are mathematically strong and secure, the underlying hardware (CMOS) implementations may reveal the secret key of the device by exhibiting data or operation dependent power consumption. Attack methodologies that use information like power consumption, timing information and electromagnetic radiation of the Cryptographic IC to find the secret key of the device are called Side Channel Attacks.Differential Power Analysis (DPA) is a category of Side Channel Attack that uses differences in power consumed for different input vectors along with statistical analysis to reveal the secret key in the device. DPA attacks are possible due to the data dependent power consumption of the CMOS circuits. Several algorithmic, circuit and logic level countermeasures have been proposed to resist DPA attacks. Unfortunately many of these techniques are either ineffective or end up having a huge overhead in other design metrics like area, power and speed. The objective of DPA resistance is to remove data dependence from power consumed. Recently, many circuit design techniques based on Dynamic and Differential Logic, which allows for matching power profiles regardless of input, have been proposed.In this thesis, we present a universal cell called SDMLp (Secure Differential Multiplexer Logic), based on differential pass transistor logic, to mitigate DPA attacks. A single two input SDMLp cell can be configured to perform all possible 16 two input logical operations. Employing SDMLp cells in circuit design increases the DPA resistance of the circuit by exhibiting 10 to 100 fold reduction in instantaneous power variance compared to existing DDL based secure logic styles and nearly 1000 fold compared to SCMOS designs. Apart from improvement in instantaneous current variation, we also show nearly 60% to 70% reduction in power consumption and nearly 45% to 50% reduction in area compared to existing DDL based secure logic styles.