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Emerging trends in design of real-time digital signal processing systems indicate that in the future, a significant amount of performance improvement can be achieved using dynamically reconfigurable embedded architectures consisting of reconfigurable, general-purpose components. Although embedded real-time systems have long been prevailing in our society, no firm scientific base has been established yet to handle timing requirements in a systematic manner in real-time embedded computing. Because of this lack of the scientific base, many embedded systems have been designed in an ad hoc manner and most of them have been customized to specific applications, showing inflexibility for the other type of applications. This paper proposes a dynamically reconfigurable embedded architecture which bridges the gap between the embedded system and ASICs. This architecture combines a reconfigurable hardware processing unit with a software programmable processor. The main goal is to take advantage of the capabilities of both resources. While the processor takes care of all sequential computations the reconfigurable hardware takes specialized vector operations. With such integrated system architecture, specific properties of applications, such as parallelism, regularity of computation and data granularity can be exploited by creating custom operators, pipelines and interconnection pathways. To handle the conflicting requirements of being a flexible architecture and implement some application-specific algorithms, a dynamically reconfigurable embedded architecture is proposed. The proposed architecture consists of arithmetic operation-level configurable modules interconnected through multiple data buses that can be logically configured to form one or more pipelines before a specific application is initiated and remains unchanged till the completion of the application. This architecture is targeted at high throughput and real time signal processing applications. The idea of dynamic reconfiguration - changing a circuit while it is operating - is exploited. In particular, we illustrate how dynamic reconfiguration can achieve significant performance improvement. Key words: Reconfigurable computing, embedded system, digital signal processing, high speed architecture, INTRODUCTION The increase in circuit density and switching speed has dramatically reduced the size of computing systems. This has contributed directly to the design of high-speed computing systems, which in [...]

This research provides a blueprint for the energy efficient assessment of sensor node architectures with a couple of low-end processors and radio as well as a couple of high-ended, high-end energy-performance processor and radio systems and includes the methodologies and techniques for the assessment of power efficiency in WSNs. The presentation of an interface for a coprocessing device dynamically reconfigurable for a wireless sensor node. The hardware accelerator is tailored to manage sensor data streams which cannot be managed effectively by micro-controllers with low power. The use of reconfigurable computing mechanisms achieves high energy efficiency. The design specifics involve many, specialized and reconfigurable processing steps. The size of the reconfiguration data is reduced using several reconfiguration levels for a fast and efficient dynamic reconfiguration. The second document describes that such nodes may provide a highly dynamic range of applications from basic temperature measurement collections or motion sensing to advanced sensor data signal processing. Our model discusses trade-offs in energy efficiency in connection with which processor and radio to select for each mission. To do this we have a general Semi- Markov Decision model, one with dynamic and one with static interconnect, to optimize the asymptotic existence of two alternative designs. The resulting models are simulated and implemented in the measurements recorded on an existing two-radios platform and two processors. Our findings demonstrate how the benefits of such a system can be quantified for each component's energy consumption properties. Moreover, on the basis of our power budget estimate, we infer that, considering the energy overhead of such systems, the conception of a reconfigurable link between multiple processors and radios would result in efficiency gains. A definition of periodic dynamic reconfiguration of a limited heterogeneous data path may lead to suitable device solutions for the target domain. To respond, the effect of the overhead reconfiguration on the overall effectiveness of the device is closely observed. Our tests therefore demonstrate the low energy consumption obtained in processors and ASICs, the low reconfiguration overhead and the particular architectural area in the design space. The case study from certain papers has demonstrated that the heterogeneous cluster architecture expands the conventional parallel processor cluster with an IPA accelerator. Although programmable processors ensure programming that is legacy for simple peripherals management, the download of the data-intense and control-intensive kernels to the IPA can lead to substantially higher device level performance and energy efficiency. [ABSTRACT FROM AUTHOR]

The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion's pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP. [ABSTRACT FROM AUTHOR]