19 results on '"Ram, Mamidala Saketh"'
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2. Multi-Level, Low-Voltage Programming of Ferroelectric HfO2/ZrO2 Nanolaminates Integrated in the Back-End-Of-Line
3. Dopingless PNPN tunnel FET with improved performance: Design and analysis
4. Self-Heating in Gate-All-Around Vertical III-V InAs/InGaAs MOSFETs
5. Low-Frequency Noise in Vertical InAs/InGaAs Gate-All-Around MOSFETs at 15 K for Cryogenic Applications
6. The Effect of Deposition Conditions on Heterointerface‐Driven Band Alignment and Resistive Switching Properties
7. A 4F2 Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon
8. Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages
9. Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs With a Field Plate
10. Controlling Filament Stability in Scaled Oxides (3 nm) for High Endurance (>106) Low Voltage ITO/HfO2 RRAMs for Future 3D Integration
11. Ultra-Scaled AlOx Diffusion Barriers for Multibit HfOx RRAM Operation
12. Low-Power Resistive Memory Integrated on III–V Vertical Nanowire MOSFETs on Silicon
13. Cross‐Point Arrays with Low‐Power ITO‐HfO 2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires
14. Investigation of Reverse Filament Formation in ITO/HfO2-based RRAM
15. Submicrometer Top-Gate Self-Aligned a-IGZO TFTs by Substrate Conformal Imprint Lithography
16. Cross‐Point Arrays with Low‐Power ITO‐HfO2 Resistive Memory Cells Integrated on Vertical III‐V Nanowires.
17. Performance Investigation of Single Grain Boundary Junctionless Field Effect Transistor
18. Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis
19. Single Grain Boundary Tunnel Field Effect Transistors on Recrystallized Polycrystalline Silicon: Proposal and Investigation
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