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Using migrating crawling agents (migrants) based methods, selection and filtration of web documents can be done at web servers rather than search engine side. It helps in reducing the network load significantly, caused by the web crawlers. Since a migrant roams around the web and executes on remote platform, the security problems have become hindrance for development and maintenance of mobile agent technology. So, there is a need to develop secured migrating agents and to fix issues like maintaining security and integrity of the agent, data it carries and the remote platform on which it executes. This paper presents a remote platform oriented reliability based approach that is helpful in maintaining security and integrity of migrants as well as for data it carries and the remote platform.

In the present era, need of compact devices with low power consumption & portably has created the need of Integrated circuits and when these devices are used for signal processing, multipliers plays a vital role & has become dominant functional blocks in processors and microcontrollers. Thus it has become crucial to explore a algorithm for fast multiplier that enhance structural design to increase speed & minimize area. This paper introduces the Array, Vedic, Wallace & Dadda Algorithms & a performance comparison between them. In this manuscript simulation has been done for the mentioned algorithms for different bit lengths i.e. two, four, eight & sixteen bit on Model-Sim using VHDL language and then their implementation them on Xilinx for comparative analysis.

Regularly increasing number of the subscribers in a specific area has compelled the network providers to search for different ideas to vigorously optimise the sector for increase of coverage & capacity with the quality of service in consideration. The researches on smart antenna systems have shown that they are sufficient for providing vigorous network performance. Network providers are required to calculate the gain representing the performance that can be find out by using this smart antenna system and a detailed estimation of its propagation results is a most priority factor of consideration for the dynamic improvement of network performance. Here, in this paper we represents a detailed performance analysis of wireless network performance with the use of this smart antenna system.

In this brief, a new analytical model to compute the potential distribution in gate overlap and underlap regions of a generic double-gate (DG) MOSFET (valid for asymmetric features in front- and back-gate insulator thicknesses, gate bias, and gate work functions) for operation in the subthreshold condition is proposed. A closed form solution to 2-D Poisson's equation is obtained with approximation of parabolic potential function along vertical direction of the device. Conformal mapping technique is applied for modeling fringe electric field in the underlap regions. The proposed potential model is extended in deriving important device parameters such as threshold voltage, threshold voltage rolloff, DIBL, subthreshold swing, etc. Model predictions demonstrate that significant improvement in subthreshold operation can be achieved with 4T asymmetric underlap DG MOSFETs in comparison to 3T symmetric nonunderlap DG MOSFETs.

Large cats are vulnerable to local extinction in fragmented landscapes mainly due to large scope developmental and anthropogenic activities. Present study highlights the mortality of protected leopard's population in Uttarakhand state, north-west India. In between January 2009 to October 2010, 78 leopards have died due to various reasons accounted pri- marily for unnatural deaths. Maximum deaths occurred in between February 2009 & April 2010 and notably 37 leopards died since January, 2010. The mortality rate for females was significantly higher than for males. Notably, 11 leopards were found dead scrambled in trap and some deaths occurred while providing treatment after rescuing the animal. In addition, 21 cases of leopard's poaching (illegal wildlife trade) were also documented in between January 2009 to March 2010 in which 35 leopard's skins were recovered, which highlighted that poaching is also ongoing in some remote areas. Status of man-animal conflict in Uttarakhand is severely increasing; in between November 2000 to December 2008, 180 people died in leopard's attack, whereas 343 were injured during encounters and leopard's attacks. On the other hand, 394 leopards died due to other reasons during the said period and 50 were declared as man-eater, which were shot dead or translocated to other protected habitat. Here, we report on the mortality in protected leopard population of Uttarakhand state and conservation status. Such reports are highly required to know the status and our competence in illustrating success and failures of wildlife rescue op- erations besides in conservation of an endangered wildlife.

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.

This article focusses on the waveform analysis and crosstalk peak estimation at far-end of victim line for simultaneously switching inputs with resistive drivers. A low loss coupled transmission line-model of interconnect is used for analytical purpose. Noise peaks are estimated for the conditions when inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analysed in general with homogeneous and non-homogeneous drivers for unipolar inputs. The driver is modelled as linear resistance. Comparison of the analytical results with simulation programme with integrated circuit emphasis (SPICE)-extracted results shows that the error involved is less than 2% and 5% for in-phase and out-of-phase switching, respectively. The comparisons of analytically obtained results with SPICE simulations show that the proposed model captures noise peaks, their timings and waveform shape for all switching conditions with an average error of less than 4%.

Floral malformation caused by Fusarium mangiferae is a serious threat to mango cultivation in various countries. Different long-term measures suggested to control it were found to be unsuccessful. Present studies clearly showed strong antifungal activity of a concoction brewed from Datura stramonium, Calotropis gigantea, Azadirachta indica (neem) and cow manure (T1) followed by methanol-water (70/30 v/v) extracts of Datura stramonium, Calotropis gigantea and Azadirachta indica (T2) against Fusarium mangiferae. Optimal control of floral malformation was found in trees sprayed with T1 followed by T2 at bud break stage and again at fruit set stage when compared with the control. All the malformed buds or panicles completely dried two days after foliar spray with T1 or T2. In the trees treated with T1 at fruit set stage, flower abscission was observed from the fourth day after spraying and all flowers dropped by the ninth day without requiring any manual de-blossoming, whereas in the control, the malformed panicles remained green and competed with the growing fruits for plant nutrients. In vitro culture of fresh malformed tissues in MS media along with T1 or T2 showed no growth of any fungus in the media. However, in vitro culture of the completely dry malformed tissues in MS media after foliar treatment with T1 or T2 revealed growth of F. mangiferae on the twenty fifth day indicating that the concoction-brewed compost (T1) or methanol-water (70/30 v/v) extracts (T2) could not completely eliminate the pathogen but helped in controlling malformation by suppressing the activity of F. mangiferae. Mango trees sprayed with T1 and T2 revealed significant differences in percent fruit set and retention when compared with the control. This could be due to observed higher levels of nitrogen, phosphorus, potassium, calcium, magnesium, copper, zinc, iron and manganese in T1, followed by T2 when compared with T3 (control). Among the different fruit quality parameters analysed, the total flavonoids were found to be significantly higher in T1 and T2 when compared with T3. The study proved that the concoction-brewed compost (T1) is effective, inexpensive, easy to prepare and constitutes a sustainable and eco-friendly approach to control floral malformation in mango when it is sprayed at bud break stage and again at fruit set stage. In this present study, exogenous treatment of emerging buds with (Tc) further proved that with increase in the number of malformed panicles/tree the number of buds developing into healthy panicles/tree decrease.

PurposeThis paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects.Design/methodology/approachThe paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width.FindingsIt is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver.Originality/valueWhile designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent @p-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.

The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion.

PurposeTo analyze the effect of voltage scaling on crosstalk.Design/methodology/approachVoltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. VA (input at aggressor node A) and VB (input at victim node B) switching in same direction; VA is switching and VB at static low; VA and VB are switching in opposite direction; VA is switching and VB at static high.FindingsIt is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.Originality/valueVoltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.

PurposeIn this paper output voltage waveform of CMOS repeater driven VLSI long interconnects is analysed, for deep submicron technologies. Ramp inputs are considered in the analysis as these are more practical than step inputs.Design/methodology/approachAnalytical models are developed for the time dependence of output voltage of repeater driven interconnect loads for rising as well as falling ramp input signals. The interconnect is modelled as a resistive‐capacitive load. Various operating regions of the MOSFETs are considered in the models. Method has also been given for determining the time at which MOSFET transits from saturation to linear region.FindingsA good agreement between the analytical and SPICE results is obtained, with analytical error 3 per cent at the most. The models developed work accurately for scaled‐supply voltages too. For a repeater loaded interconnect the variation of 90 per cent delay with number of repeaters at different supply voltages has also been determined by the proposed model. It is found that the optimum number of repeaters decreases with voltage‐scaling and this decrease is technology independent.Research limitations/implicationsThe parasitic inductance component in long interconnects is not considered in this analysis.Practical implicationsThe work is useful for timing analysis of repeater driven resistive interconnects.Originality/valueA very concise analytical approach for a CMOS repeater stage timing analysis is developed.

Purpose – To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.Design/methodology/approach – Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size Wn=3.9 μm and Wp=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. VA sw...

PurposeDelay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.Design/methodology/approachTrade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.FindingsOptimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.Research limitationsThe bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.Originality/valueThe paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

Long interconnections in very large scale integration (VLSI) circuits, lead to prohibitively high propagation delays. Insertion of repeaters in long interconnects is an important technique to reduce delay. Interconnects and repeaters lead to high power dissipation too. The parameters controlling the performance of complementary metal oxide semiconductor (CMOS) inverting repeaters driving interconnect loads have been recognized in this paper. A scheme for optimization of the repeater-chain loaded long interconnects is proposed. Optimization of the transistor channel width supply voltage and the number of repeaters to be inserted in a long interconnect has been carried out by SPICE simulations. Empirical relations are proposed for optimal values of the parameters. Simulation results validate the effect of the controlling parameters on the performance of CMOS repeater-chain driven long interconnects. The analysis has been carried out for six deep submicron technologies viz. 0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm...

This paper deals with the studies carried out on sensitivity, response and recovery time of a sensor array comprising of undoped and doped (palladium, platinum and gold) thick-film SnO 2 sensors. Initially, the sensitivity of all the sensors of the array has been studied for H 2 , CO, CH 4 and LPG followed by detailed analysis of transient response of Pd-doped sensors as it possesses better sensitivity for all the test gases. The response and recovery time of the Pd-doped sensor has been found to depend on type of gas and its concentration (upto 400 ppm). The response time is minimum for CO and maximum for H 2 while recovery time is maximum for LPG and approximately same for H 2 and CO. The observed results of response time have been explained on the basis of two-film theory, i.e. gas film-gas phase and solid-gas film interfaces. Further, the experimental result of the sensor array (sensitivity versus concentration and sensitivity versus response time) for all the test gases at an operating temperature of 350°C have been validated with an analytical model and the observed results are found to be in good agreement to that predicted by the model.

This paper gives an insight of e-commerce and highlights the present scenario of e-commerce in India. It presents the surfing pattern of Indian public to give the critical review on truth of various reports being published from time to time. It also critically analyses the e-commerce with major focus on B2C e-commerce which involves e- tailing. Index Terms—e-Commerce, B2C, e-tailing, Indian Consumer, Trust

Due to the dynamic nature of the web, it becomes very difficult for a search engine to provide fresh information to the user. An incremental crawler downloads modified contents only from the web for a search engine, thereby helps reducing the network load. This network load further can be reduced by using migrants. The migrants migrate to the web server for the purpose of downloading, filtering and compressing the documents before transferring them to the search engine side. In this paper a more network efficient approach for extracting the volatile information from the web server using migrants has been developed with the help of table of volatile information, which further helps in reducing the network load significantly.

The present study describes the effect of electrode material on the performance of a screen-printed thick-film SnO 2 gas sensor. The response of the sensor, i.e., the percentage change in the sensor resistance upon exposure to H 2 , CO and CH 4 , has been studied for two different electrodes of silver and gold. It has been observed that the sensitivity of the thick-film SnO 2 sensor for H 2 and CO with silver (Ag) is much higher (about 65.5% and 42.6%, respectively) as compared to the Au-electode sensor. A possible mechanism for the higher sensitivity of the Ag-based SnO 2 sensor has been suggested in terms of autodoping at the time of firing of the SnO 2 layer. The idea of autodoping has been confirmed by performing Ag doping of SnO 2 (with a Au electrode) and studying its performance.

A thick-film SnO2-based hydrogen gas sensor has been developed. The fabricated device is found to be very sensitive for hydrogen gas and is capable of detecing hydrogen in the order of a few ppm (⩽100) concentration. The effects of temperature and the amount of catalytic palladium doping in SnO2 towards the hydrogen sensitivity of the sensor have been studied. The peak sensitivity of the sensor towards hydrogen is found to be at an operating temperature of 350 °C and the optimum catalytic content in the SnO2 layer is 0.25 wt.% palladium. A possible reaction scheme for the interaction of hydrogen with the SnO2 surface in air is also proposed.

Study reports that about 40% of current internet traffic and bandwidth consumption is due to the web crawlers that retrieve pages for indexing by the different search engines. As the size of the web continues to grow, searching it for useful information has become increasingly difficult. The centralized crawling techniques are unable to cope up with constantly growing web. In this paper it is presented that distributed crawling methods based on migrating crawlers are an essential tool for allowing such access that minimizes network utilization and also keeps up with document changes.

Asymmetric and independent gate features of DGMOSFETs are explored recently for nano scale applications. This paper investigates minimization of short channel effects based on the independent gate, gate-S/D under lap and asymmetric (in front and back gate oxide thickness, gate work functions and gate bias) features of DGMOSFETs. Novel analytical models for threshold voltage, threshold voltage roll-off and DIBL effects of an under lap DGMOSFET with asymmetric, independent gate features are proposed and validated with numerical simulation results. Overall, results show that gate under lap feature and asymmetry brought in DGMOSFET by proper tuning of back gate bias, back gate oxide thickness and gate work function materials add more flexibility for tuning of DGMOSFET device threshold voltage and minimizing SCEs which are not available in tied gate symmetric DGMOSFETs.

Every communication receiver that uses in-phase and quadrature channel signal processing technique encounters problems related to matching of gain and phase in both the channels. The gain and phase imbalances occur between Low Pass Filter and Local Oscillator used in both the channels and as a result the performance of the receivers and the quality of the received signals are degraded. The imbalances produced may cause insufficient attenuation in image frequency band leading to interference. The problem needs to be compensated. This paper represents the design and implementation of Coordinate Rotation Digital Computer (CORDIC) algorithm based Adaptive FIR filter using Least Mean Square (LMS) algorithm to give a solution for correcting I/Q imbalances. The design of CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage and finds its appropriate application in real time signal processing. The good convergence of CORDIC in the given LMS algorithm based adaptive filter facilitates in easy calculation of new filter weights.

A novel analytical model for subthreshold current of a generic double-gate MOSFET (DGMOSFET) with gate-to-source/drain underlaps is proposed. The accuracy of the new model is verified based on comparisons with previously published models and numerical simulation results. With the proposed current model, effectiveness of back gate biasing, back gate asymmetry, gate work function engineering, and gate underlap engineering techniques are evaluated for suppressing the subthreshold leakage currents. Independent gate bias with gate underlap engineering significantly reduces subthreshold leakage currents as compared to standard tied- gate DGMOSFETs.

A novel analytical model for subthreshold slope of a generic double-gate MOSFET (DGMOSFET) with gate-to-source/drain underlap is proposed. The accuracy of the new model is verified based on comparisons with previously published models, experimental data and numerical simulation results. With the reduction in body thickness, an improvement in underlap independent gate (4T) DGMOSFET subthreshold slope value is observed, particularly as back gate oxide asymmetry would increase in comparison to that of front gate oxide thickness. Models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

Digital Signal Processing (DSP) systems involve a wide spectrum of DSP algorithms and their realizations are often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal processors or on application specific VLSI chips. This paper presents the design of Adaptive Finite Impulse Response (FIR) filter for moving target detection in various clutter conditions in Radar Receiver. The design uses pipelined COordinate Rotation DIgital Computer (CORDIC) unit and pipelined multiplier to get high system throughput and reduced latency in each of the pipelined stage. Saving area on silicon substrate is essential to the design of any pipelined CORDIC. The area reduction in proposed design can be achieved through optimization in the number of micro rotations. For better adaptation and performance of Adaptive Filters and to minimize quantization error, the numbers of iterations are also optimized.

Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. This paper presents the design of pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver. The design of CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in proposed design can is achieved through optimization in the number of micro rotations. For better loop performance of first order complex DPLL and to minimize quantization error, the numbers of iterations are also optimized.

Laminar non-Newtonian power-law fluid flow development in a pipe has been obtained by studying a hydrodynamically equivalent Newtonian analogue of the problem. Several integral solutions of the problem have been presented and their predictions have been compared with another similar solution.

A method is proposed here for development of a new tool which provides fast and efficient way for fault diagnoses in analog CMOS circuits arises due to glitches. The tool follows SBT (simulation before testing) based approach for tests the CMOS analog circuits against faults arises due to glitches. SBT system for fault diagnosis requires some form of a fault dictionary to which the test data is compared. The designed tool generates a fault dictionary which is used in SBT method with distinct pretest and post-test analysis stages. Pretest analysis generates a fault directory. For this the circuit is simulated circuit under all fault combinations, as well as the fault-free case. We can then compute observable variables (voltages or currents), of them, for each combination and store them in an entry of the fault directory.

This paper deals with crosstalk analysis of a CMOS gate driven capacitively and inductively coupled interconnect. Alpha Power Law model of MOS - transistor is used to represent a transistor in CMOS- driver. This is combined with a transmission line based coupled RLC-model of interconnect to develop a composite driver interconnect load (DIL) model for analytical purpose. On this basis a transient analysis of crosstalk noise is carried out. Comparison of the analytical results with SPICE extracted results shows that the error involved is nominal.

This paper deals in waveform analysis, crosstalk peak and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Peaks and delays at far-end of victim line are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analyzed in general with homogeneous and non-homogeneous drivers for unipolar inputs. Alpha Power Law model of MOS-transistor is used to represent the transistors in CMOS-driver. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy.

This paper focuses on waveform analysis and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Delays at far-end of victim are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase and out-of-phase. Alpha Power Law model of MOS-transistor is used to represent the transistors in CMOS-driver. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures 90% propagation delay; transition time delay and waveform shape with good accuracy.

This paper focuses on waveform analysis and crosstalk peak estimation at far-end of victim line for simultaneously switching inputs with resistive drivers. A transmission line based low loss coupled ALC-model of interconnect is used for analytical purpose. Positive and negative peaks are estimated for the conditions when inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analyzed in general with homogeneous and non-homogeneous drivers for unipolar inputs. The driver is modeled as linear resistance. Comparison of analytical results with SPICE extracted results shows that the error involved is less than 2% and 5% for in-phase and out-of- phase switching respectively. The comparisons of analytically obtained results with SPICE simulations show that the proposed model captures noise peaks and waveform shape quite well.

The equivalent electrical circuit model of a bundled single-walled carbon nanotube based distributed RLC interconnects is employed for the crosstalk analysis. The accurate time domain analysis and crosstalk effect in the VLSI interconnect has emerged as an essential design criteria. This paper presents a brief description of the numerical method based finite difference time domain (FDTD) technique that is intended for estimation of voltages and currents on coupled transmission lines. For the FDTD implementation, the stability of the proposed model is strictly restricted by the Courant condition. This method is used for the estimation of crosstalk induced propagation delay and peak voltage in lossy RLC interconnects. Both functional and dynamic crosstalk effects are analyzed in the coupled transmission line. The effect of line resistance on crosstalk induced delay, and peak voltage under dynamic and functional crosstalk is also evaluated. The FDTD analysis and the SPICE simulations are carried out at 32 nm technology node for the global interconnects. It is observed that the analytical results obtained using the FDTD technique are in good agreement with the SPICE simulation results. The crosstalk induced delay, propagation delay, and peak voltage obtained using the FDTD technique shows average errors of 4.9%, 3.4% and 0.46%, respectively, in comparison to SPICE.