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In this paper, we present an electronic readout system for wireless passive sensors based on inductively coupled LC resonant circuits. The proposed system consists of a reader coil inductively coupled to the sensor circuit, an analog frontend circuit, and a digital signal processing unit. The analog frontend circuit generates a dc voltage representing the sensor resonance curve. The frequency of the reader coil driving signal is continuously readjusted by the digital signal processing unit. Based on analytical calculation and system simulation, we derive a model for the achievable accuracy of the overall sensor and readout system. The accuracy is limited by noise and systematic errors due to the measurement principle. We show how to design the digital signal processing system for optimal insensitivity to voltage noise. The noise sensitivity of the measurement system is inversely proportional to the square of the quality factor of the LC sensor. This means that minimizing the losses of the sensor is of crucial importance to obtain a wireless measurement system with a high range and a good insensitivity to noise. Subsequently, we outline an approach to calculate the sensor resonance frequency, quality factor, and inductive coupling factor from the available voltage signals in the signal processing unit using linear fitting functions. The accuracy of our approach is exemplified by a system simulation for typical sensor parameters. For the system studied, we show that the relative linearization error of the sensor resonance frequency measurement is below 0.02%. Taking the general models presented for both the noise sensitivity and linearization error into account, it is possible to estimate the maximum distance and accuracy for any wireless sensor system based on an inductively coupled LC resonator.

This paper reports simple yet precise equations for automated wireless measurement of the resonance frequency, Q-factor, and coupling coefficient of inductively coupled passive resonant LC circuits. This allows remote sensing of all physical and chemical quantities that can be measured with capacitance transducers. Formerly reported front-end circuit concepts for wireless sensor readout, i.e., phase dip measurement and the dip meter, are subsequently discussed. It is shown that, due to fundamental system limitations, the formerly reported circuit concepts are not applicable if the distance between the sensor and the readout electronic circuit becomes too small, resulting in large coupling coefficients. Therefore, we present an improved concept for an analog front-end circuit of the readout system that overcomes these limitations and hence allows wireless sensor readout under a wider range of operating distances.

Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

Selbstorganisierte, dezentrale Materialflusssysteme – das Internet der Dinge in der Intralogistik – konnen uber den Lebenszyklus deutliche Vorteile gegenuber herkommlichen, zentral gesteuerten Systemen aufweisen. Neben der durch den modularen Aufbau der Steuerung erleichterten Inbetriebnahme ergeben sich auch Vorteile, die erst spater zum Tragen kommen: Relevant sind dabei vor allem eine erhohte Flexibilitat bezuglich Anderungen und Erweiterungen, eine hohere Robustheit und die durch den Einsatz von RFID bedingte Verfugbarkeit von Echtzeitdaten uber das System. Der vorliegende Beitrag geht nach einer kurzen Einfuhrung auf diese Vorteile ein. Vor allem die erhohte Flexibilitat durch den modularen Aufbau der Steuerung verspricht deutliche Vorteile uber den Lebenszyklus – fur diese wird daher eine mogliche Bewertungsmethodik vorgestellt und erlautert.

Implementing arithmetic-heavy applications such as filters or neural networks in FPGAs relies to a great extent on the realization of efficient multipliers. However, implementing high-precision multipliers only with configurable logic leads to a large lookup-table usage and considerable routing efforts. Thus, hard-wired multiplier blocks are embedded in modern FPGA devices in order to relieve the resources, but their word-length is still fixed to e.g. 18x18-bit in the Xilinx Virtex-IV DSP48 slices. In this paper, we describe our approach of creating configurable blocks suitable for multi-precision multiplication with a word-length that can be changed at runtime. We present a novel block-serial design that shows a 60 % area advantage over a fully parallel multiplier and also a larger structure that can be partitioned into several fully functional smaller multipliers working simultaneously in different configurations.