Search

Goals: The purpose of this study was to analyze the feasibility of using the information obtained from a one-channel electro-encephalography (EEG) signal to control a mouse pointer. We used a low-cost headset, with one dry sensor placed at the FP1 position, to steer a mouse pointer and make selections through a combination of the user’s attention level with the detection of voluntary blinks. There are two types of cursor movements: spinning and linear displacement. A sequence of blinks allows for switching between these movement types, while the attention level modulates the cursor’s speed. The influence of the attention level on performance was studied. Additionally, Fitts’ model and the evolution of the emotional states of participants, among other trajectory indicators, were analyzed. (2) Methods: Twenty participants distributed into two groups (Attention and No-Attention) performed three runs, on different days, in which 40 targets had to be reached and selected. Target positions and distances from the cursor’s initial position were chosen, providing eight different indices of difficulty (IDs). A self-assessment manikin (SAM) test and a final survey provided information about the system’s usability and the emotions of participants during the experiment. (3) Results: The performance was similar to some brain–computer interface (BCI) solutions found in the literature, with an averaged information transfer rate (ITR) of 7 bits/min. Concerning the cursor navigation, some trajectory indicators showed our proposed approach to be as good as common pointing devices, such as joysticks, trackballs, and so on. Only one of the 20 participants reported difficulty in managing the cursor and, according to the tests, most of them assessed the experience positively. Movement times and hit rates were significantly better for participants belonging to the attention group. (4) Conclusions: The proposed approach is a feasible low-cost solution to manage a mouse pointer

A novel low voltage tunable linear transconductor is presented. The approach is based on quasi-floating gate transistors achieving higher transconductance and better dc common mode rejection than previous implementations. A dynamic biasing technique improves the sensibility of the linearity to process variations. Measurement results of the circuit, designed in a 0.5 μm CMOS process from 1.4 V power supply, confirm the advantages of the proposed approach with a very high speed operation of 50 MHz of gain-bandwidth product, a IM3 of ?40 dB and a nominal power consumption of only 490 μW.

This paper presents a design of low power and low noise, high speed readout front-end system for semiconductor detectors. The architecture comprises a folded cascode charge sensitive amplifier with gain enhancement, a pole-zero cancellation circuit and a complex shaper circuit with Gm-C topology. A local feedback amplifier based on a wide swing gain boosting scheme with dc level shifting has been used. The system has been fabricated in a 0.13-µm CMOS technology with a single 1.2-V supply voltage. Experimental results show the flexibility of the system where the key parameters, such as decay time, charge gain and peaking time can be tuned. For a nominal peaking time of 150 ns the power consumption of the entire channel is less than 5 mW. A power consumption-low noise tradeoff will be considered to match a detector capacitance of 5 pF. The output pulse has a peak amplitude of 200 mV for a charge of 10 fC from the detector and achieves a linearity better than 1% up to an input charge range of 12 fC.

A high speed, low power and programmable readout front-end system is presented for silicon detectors to be used in nuclear physics applications. The architecture consists of a folded cascode charge sensitive amplifier, a pole-zero cancellation circuit to eliminate undershoots and a shaper circuit with Gm-C topology. All building blocks include a regulated cascode technique based gain enhancement. Experimental results show that the whole front-end system can be programmed for peaking times of 100 ns, 200 ns and 400 ns maintaining the amplitude of the output voltage. Programmability is achieved by switching different resistors for all poles and zeros. The system has been designed in a 130 nm CMOS technology and powered from a 1.2 V supply. The output pulse has peak amplitude of 200 mV for an input energy of 5 MeV from the detector. A power consumption low noise tradeoff will be considered.

A strategy is presented to evaluate the statistical means and standard deviations of the transient characteristics of CMOS analog cells. Based upon the Monte Carlo analysis of electrical simulations, this strategy follows a circuit-theory based approach achieving an important reduction on matrix ranges and consequently on the number of operations involved in the resolution of the circuit. The CPU time-consuming reduction is achieved also by saving information corresponding to the nominal transient analysis. We include comparative results for several CMOS cells showing the advantages of the proposed strategy.

This paper presents a design of a single readout front-end channel for energy spectroscopy. The front-end electronic system comprises a charge sensitive amplifier and a pulse shaping amplifier. Novel techniques based on regulated cascode circuits to increase the gain are proposed. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. The analog system has been designed in a 90 nm technology and optimized to match a detector capacitance of 5 pF. Simulation results confirm the advantages of the proposed approaches in terms of gain, speed, linearity and power consumption.

A technique is presented to evaluate mean values and standard deviations of transient analog cell specifications under random fluctuations of the primitive component parameters. Its precision and generality are similar to those of Monte Carlo analysis of electrical simulations while its CPU time is considerably smaller. The advantages of the proposed technique are demonstrated via the statistical evaluation of two CMOS cells.

A set of novel techniques are implemented in a CAD tool, FASTEST, which achieves more than one order of magnitude CPU time reduction in typical statistical electrical evaluation of AC and now transient and DC specifications of analog circuits, A description of techniques for DC specifications is presented herein. The tool performance is demonstrated via the analysis of a multiple current mirror. The CPU time is reduced by one order of magnitude with respect to conventional Monte Carlo simulation, while maintaining similar accuracy in the computations.