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Despite of the fact that thousands of CD-SEM (critical dimension scanning electron microscope) images are acquired in a daily basis in a fab, limited metrology is performed. Usually these images will not serve other purposes after they are collected and measured, but as they are stored, post-process analysis can be applied. Initially, most of these images are used to perform CD metrology, even though many other types of metrics could be extracted from the same images, especially when using contour metrology. In this paper two use cases will be explored, where contour-based image processing is performed on typical inline metrology targets. In both cases, initial intended metric was CD but thanks to contour based image computing, complementary information can be extracted. In the first use case, CD and overlay metrics can be extracted, while in the second CD, etch slanting and asymmetry analysis is performed across the wafer. Contour-based metrology offers new capabilities to dissociate several layers (e.g. via and line) or elements (e.g. top and bottom) in the image so that interlayer and intralayer metrics, other than width dimensions, can be computed. Besides, a solution not integrated in the tool provides excellent versatility to re-process images, thus allowing the obtention of new metrics, which can be very helpful also for retro-analysis.

Galileo Galilei once quoted: “Measure what is measurable, and make measurable what is not so”. In silicon manufacturing R&D phase, it often happens that engineers would like to access some parameter values that are not easy, even impossible to measure. When looking at a CDSEM image, the parameters of interest seem easy to extract but in practice getting access to them in a robust and reliable way is not always simple. Developing a contour-based metrology tool coupling robust contour extraction with a comprehensive contour metrology environment could help to bridge this gap. In previous works, it has been shown that SEM images contain significant amounts of information that can be extracted and analyzed using efficient contour extraction and analysis toolboxes [1, 2]. Also, the concept of implementing remote contour-based metrology has been introduced. The present work continues to unveil what can be achieved with such solutions. For that, the example of implant layers’ process assumption will be explored. During this process step, counter doping problems can occur for example when the distance between layers deviates from nominal. Therefore, it is crucial for design rule control to measure some critical dimensions such as minimum distance between layers, corner rounding, slope, etc. However, given the characteristics of the different structures in the images, which may come from different layers and/or processes steps, the measurements are not straightforward to extract with standard CDSEM metrology algorithms. Moreover, recipes are complex to setup, measurements by themselves are not very stable, and usually an indirect determination of the key figure is performed. In this paper, we will show that multilayer contour-based metrology, mixing image contour and GDS layout, allows to overcome the previously mentioned difficulties, as well as to generate measurements that are not possible to be performed by using standard algorithms.

In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted. This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox. Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.

With these proceedings we present μ-diffraction-based overlay (μDBO) targets that are well below the currently supported minimum size of 10×10 μm2 . We have been capable of measuring overlay targets as small as 4×4 μm2 with our latest generation YieldStar system. Furthermore we find an excellent precision (TMU < 0.33 nm for 6 × 6 μm2 ) without any compromise on throughput (MAM time < 60 ms). At last a study that compares four generations of YieldStar systems show clearly that the latest generation YieldStar systems is much better capable of reading small overlay targets such that the performance of a 16 × 16 μm2 on an early generation YieldStar 2nd-gen is comparable to that of a 8 × 8 μm2 on the latest YieldStar 5th-gen. This work enables a smaller metrology footprint, more placement flexibility and in-die overlay metrology solutions.

Continuous tightening of the overlay control budget in the semiconductor industry drives the need for improved overlay metrology capabilities. In this context, measurement accuracy needs to be addressed. The first part this study shows that Diffraction Based Overlay metrology accuracy can be improved with a dedicated methodology. This methodology involves the use of target design simulation software in order to maximize stack sensitivity and to minimize processes non uniformity impact on the measurement. In the second part this study focuses on Holistic Metrology Qualification (HMQ) methodology that allows selecting the best on-wafer target. The methodology is explained and discussed. It is demonstrated that HMQ helps to reduce target asymmetry impact on measurement uncertainty and to select primary recipe parameters (wavelength, polarization, etc…). Finally CD-SEM measurements were used to validate methodology results.

This work focuses on the formation of residues that grow on a metallic-hard mask after etching of porous low-k materials in fluorocarbon-based plasmas. The residue growth, which is dependent on the air exposure time after etching, causes line and via opens that strongly impact the yield performance. The different elements which could play a role in the chemical reactions have been clarified. The authors have demonstrated that in their experimental conditions, after fluorocarbon etching and air exposure, the oxidized titanium nitride reacts with fluorhydric acid to form metallic salts. This is a reaction between fluorine from the reactive layer formed on titanium nitride and hydrogen coming from the atmosphere. This reaction is all the more fast because the titanium nitride is oxidized.

Patterning process control of advanced nodes has required major changes over the last few years. Process control needs of critical patterning levels since 28nm technology node is extremely aggressive showing that metrology accuracy/sensitivity must be finely tuned. The introduction of pitch splitting (Litho-Etch-Litho-Etch) at 14FDSOInm node requires the development of specific metrologies to adopt advanced process control (for CD, overlay and focus corrections). The pitch splitting process leads to final line CD uniformities that are a combination of the CD uniformities of the two exposures, while the space CD uniformities are depending on both CD and OVL variability. In this paper, investigations of CD and OVL process control of 64nm minimum pitch at Metal1 level of 14FDSOI technology, within the double patterning process flow (Litho, hard mask etch, line etch) are presented. Various measurements with SEMCD tools (Hitachi), and overlay tools (KT for Image Based Overlay – IBO, and ASML for Diffraction Based Overlay – DBO) are compared. Metrology targets are embedded within a block instanced several times within the field to perform intra-field process variations characterizations. Specific SEMCD targets were designed for independent measurement of both line CD (A and B) and space CD (A to B and B to A) for each exposure within a single measurement during the DP flow. Based on those measurements correlation between overlay determined with SEMCD and with standard overlay tools can be evaluated. Such correlation at different steps through the DP flow is investigated regarding the metrology type. Process correction models are evaluated with respect to the measurement type and the intra-field sampling.

Critical dimension and overlay measurements have become a key challenge in microelectronics process control, and the weight of metrology in the success of a patterning technique is increasing. For the 14 nm node, the limit of scanner resolution can be overcome by double patterning, which requires a maximum overlay variability of 3 nm between the two reticles of the first metal level. In the double patterning case of metal layers, critical dimension of line spaces and overlay are no longer independent. In this paper, the possibility of a common measurement after the second lithography is studied. Scatterometry has been used to fit successfully the critical dimension of the two sublevels. As sensitivity to overlay is too low in device-like target, a strategy has been implemented from diffraction-based overlay measurement. So it becomes possible to provide information on the lithography step quality before the second etch process to enable rework if necessary. Finally a scatterometry target has been designed to fit simultaneously the two critical dimensions and overlay. This target, which is designed to maximize overlay sensitivity, has been placed in the next 14 nm CMOS product and is expected to make this scatterometry method even more attractive.

In microelectronics the two crucial parameters for the lithography step are the critical dimension, which is the width of the smallest printable pattern, and the misalignment error of the reticle, called overlay. For the 14 nm node, the limit of scanner resolution can be overcome by the double patterning technique, which requires a maximum overlay error between the two reticles of 3 nm [1] . The current approach in the measurements of critical dimension and overlay is to treat them separately, but it has become much more complex in the double patterning context, since they are no longer independent. In this paper, a strategy of a common measurement is developed. The aim of the strategy is to measure simultaneously overlay and critical dimension in the metal level double patterning grating before the second etch process. The scatterometry technique is well known for critical dimension measurement. This study demonstrates that the overlay between the two gratings can also be deduced. Thanks to this original scatterometry-based method, it becomes possible to provide information on the lithography step quality before the second etch process; therefore the lithography can be reworked if it is necessary.

The manufacturing of next generation semiconductor devices forces metrology tool providers for an exceptional effort in order to meet the requirements for precision, accuracy and throughput stated in the ITRS. In the past years hybrid metrology (based on data fusion theories) has been investigated as a new methodology for advanced metrology [1][2][3]. This paper provides a new point of view of data fusion for metrology through some experiments and simulations. The techniques are presented concretely in terms of equations to be solved. The first point of view is High Level Fusion which is the use of simple numbers with their associated uncertainty postprocessed by tools. In this paper, it is divided into two stages: one for calibration to reach accuracy, the second to reach precision thanks to Bayesian Fusion. From our perspective, the first stage is mandatory before applying the second stage which is commonly presented [1]. However a reference metrology system is necessary for this fusion. So, precision can be improved if and only if the tools to be fused are perfectly matched at least for some parameters. We provide a methodology similar to a multidimensional TMU able to perform this matching exercise. It is demonstrated on a 28 nm node backend lithography case. The second point of view is Deep Level Fusion which works on the contrary with raw data and their combination. In the approach presented here, the analysis of each raw data is based on a parametric model and connections between the parameters of each tool. In order to allow OCD/SEM Deep Level Fusion, a SEM Compact Model derived from [4] has been developed and compared to AFM. As far as we know, this is the first time such techniques have been coupled at Deep Level. A numerical study on the case of a simple stack for lithography is performed. We show strict equivalence of Deep Level Fusion and High Level Fusion when tools are sensitive and models are perfect. When one of the tools can be considered as a reference and the second is biased, High Level Fusion is far superior to standard Deep Level Fusion. Otherwise, only the second stage of High Level Fusion is possible (Bayesian Fusion) and do not provide substantial advantage. Finally, when OCD is equipped with methods for bias detection [5], Deep Level Fusion outclasses the two-stage High Level Fusion and will benefit to the industry for most advanced nodes production.

Planar Fully-Depleted (FD) Silicon On Insulator (SOI) MOSFET technology has already demonstrated large performance boost vs bulk at 28nm node (>30%) and is very competitive for incoming mobile & multimedia products thanks to design porting from bulk. Indeed, FDSOI is very attractive for low power applications due to its low sub threshold slope (~60mV/dec), better short channel effect (SCE) control and reduced junction capacitance. 28nm FDSOI devices highly depend on gate CD morphology because electrical effective gate length is driven by metal gate CD. High-k metal gate etching is therefore a key point to achieve these requirements. Gate profiles and metal gate CD control are mandatory and variability has to be minimized across the wafer (WiW), wafer to wafer and lot to lot. In this paper, we will focus on metal gate CD variability investigation. Once polysilicon gate profiles are frozen, metal gate profiles adjustment is achieved, based on scatterometry metal gate profiles measurements, TEM analysis and electrical results. Thanks to this methodology, a metal gate etching process has been tuned on 300mm industrial platform etcher. This work was performed at ST Crolles 300 facility in collaboration between STMicroelectronics & CEA/LETI.

Current process tool performances are getting significantly enhanced by the adoption of advanced process correction application such as DoseMapper for CD or high order overlay correction for overlay. These process control capabilities need appropriate sampling to be efficient. Usually for in field metrology sampling we used to operate with metrology targets placed inside the scribe lines, however in this case the larger the chip the less scribe lines we have and the less relevant is the intrafield sampling. As ST is an IDM we have the opportunity to share with our design division this process control problematic. Since 45/40nm node we have started to put in place the so-called EMET (Embedded Metrology Target) strategy which consists in in-design metrology targets placement. Initially these targets were placed using tiling tools but it soon appeared to be not efficient and even impossible when we talk about targets involving complex metal stack. This papers talks about our current embedded metrology target strategy which has been adapted to enable appropriate target placement for CD and overlay for all critical layers from active to via/metal’s. Solutions needed to be put in place to (i) keep the circuit safe by using Design Rule clean metrology targets, (ii) be highly visible by the designers by placing targets at chip floor planning definition (iii) be upgradable by enabling target re-designs without impact on chip design version.

Gate patterning control for 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology faces several challenges. For lithography and etch , usage of DoseMapper requires extensive and accurate metrology to compute adequate dose recipes. From etch side we will have to control both polysilicon and metal gate CD’s. For device integration it will be extremely important to monitor N and PMOS devices and get appropriate gate profiles since transistor morphology is a key contributor to device performances. In parallel of CD control, thin silicon film on top of buried oxide layer will also require a strict control of its thickness. Scatterometry is the only way to get all these informations from a patterned environment [1]. We will show in this paper how scatterometry has been proven to be accurate enough to support the realization of DOE’s for metal gate profile optimisation at gate patterning without doing hundred’s of TEM. Scatterometry results are correlated to parametric tests and TEM for ultimate validation.

We introduced a simple method based on scatterometry measurement performed on dense contact holes matrix to investigate intrafield focus deviation on 28nm FDSOI real production wafers at contact holes patterning lithography operation. A complex three-dimensional scatterometry model with all patterned resist geometrical parameters left as degree of freedom. Then simple linear relationships between patterned resist geometrical parameters on the one hand, and applied dose and focus offset on the other hand were used to determine a focus and dose decorrelation model. This model was then used to investigate the effect of ASML AGILETM scanner option on intrafield focus deviation. A significant 16% intrafield focus standard deviation improvement was found with AGILETM, which validated our method and shows the possibilities of AGILETM option for intrafield focus control. This focus investigation method may be used to improve advanced CMOS manufacturing process control.

The main difficulty related to DoseMapper correction is to generate an appropriate CD datacollection to feed DoseMapper and to generate DoseRecipe in a user friendly way, especially with a complex process mix. We could heavily measure the silicon and create, in feedback mode, the corresponding DoseRecipe. However, such approach in a logic fab becomes a heavy duty due to the number of different masks / product / processes. We have observed that process CD variability is significantly depending on systematic intrawafer and intrafield CD footprints that can be measured and applied has generic pre-correction for any new product/mask process in-line. The applied CD correction is based on a CD (intrafield: Mask + Straylight & intrawafer: Etch Bias) variability "model" handled by the FAB APC (Advanced Process Control). - Individual CD profile correction component are generated "off-line" (1) for Intrafield Mask via automatic CD extraction from a Reticle CD database (2) for Intrafield Straylight via a CD "model" (3) for Intrawafer Etch Bias via engineering input based on process monitoring. - These CD files are handled via the FAB APC/automation system which is remotely taking control of DoseMapper server via WEB services, so that CD profiles are generated "off-line" (before the lot is being processed) and stored in a profile database while DoseRecipes are created "real-time" on demand via the automation when the lot comes to the scanner to be processed. DoseRecipe and CD correction profiles management is done via the APC system. The automated DoseRecipe creation is now running since the beginning of 2011 contributing to bring both intrafield and intrawafer GATE CDu below 1nm 3sigma, for 45/40 & 28nm nodes.

International audience; The choice of copper/low-k interconnect architectures is instrumental in achieving high device performances. Today, the implementation of porous low-k materials becomes mandatory in order to compensate metal resistance increase upon RC product. However, their introduction, which was initially planned for the 65nm technological node, was delayed to 45nm node due to integration issues. Using an integration strategy which combines porous SiOCH materials and metal hard masks, the difficulties and possible solutions are presented in this paper with emphasis on plasma etching.

Improving Integrated Circuits performance requires the use of porous SiCOH in interconnects. However, porosity leads to plasma species diffusion into the material during the patterning steps, which damages the low-k properties. Characterizing plasma-damaged porous SiCOH is not straightforward, and requires a specific characterization setup and protocol. In this paper, we show the impact of the ambient atmosphere on the low-k properties, and how it should be taken into account during the characterization of plasma-damaged porous SiCOH.

Porous materials such as ultra low-k dielectrics are commonly used in micro and nano technologies. Since porosity leads to an increased sensitivity of the material to etching and post-etching plasma processes, porosity, pore size and surface modifications need to be assessed during material integration. In this work, the recently developed Scatterometric Porosimetry technique using a porosimetry acquisition coupled with a scatterometric analysis is applied to measure the properties of porous patterned layers. Measurements are performed on specially fabricated gratings after exposure to different plasma treatments. A side-by-side comparison between Ellipsometric Porosimetry and Scatterometric Porosimetry is carried out on different plasma-treated samples and shows a different impact of the plasma processes on patterned materials compared with blanket films. These results highlight the interest of Scatterometric Porosimetry to characterize sidewall damage after each step of the process. It also appears as a good complementary technique to Ellipsometric Porosimetry which only allows quantitative measurements on continuous layers.

International audience; The use of a metallic hard mask approach for porous dielectric film integration implies for patterning processes, different difficulties like dimensional control, bottom line roughness and residue formation or chamber conditioning. In this paper we propose to present these issues and associated solutions for p-SiOCH integration in dual damascene structure using a trench first metallic hard mask approach.

International audience; For the sub-32 nm node, porous SiCOH dielectrics (p-SiCOH) are integrated using dual damascene patterning by etching trenches and vias into the porous material. One challenge is to control the process conditions to minimize the plasma-induced damage of p-SiCOH materials at the bottom and at the sidewall of the trenches. Ellipsometric Porosimetry has been adapted to characterize the plasma-treated materials for both horizontal and vertical surfaces. Since surface modifications can cause adsorption and desorption delays and hydrophobicity loss, porosimetry measurements operated with multi-solvent and kinetic protocols are required. Quantitative measurements of vertically patterned materials are demonstrated using periodic structures of porous material and a Scatterometric Porosimetry analysis. Results show a good sensitivity of the measurement to the different process conditions but also highlight a different impact of the plasma processes on patterned materials compared with blanket films.

With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.

International audience; Porous SiCOH materials integration for integrated circuits faces serious challenges such as roughening during the etch process. In this study, atomic force microscopy is used to investigate the kinetics of SiCOH materials roughening when they are etched in fluorocarbon plasmas. We show that the root mean square roughness and the correlation length linearly increase with the etched depth, after an initiation period. We propose that: (1) during the first few seconds of the etch process, the surface of porous SiCOH materials gets denser. (2) Cracks are formed, leading to the formation of deep and narrow pits. (3) Plasma radicals diffuse through those pits and the pore network and modify the porous material at the bottom of the pits. (4) The difference in material density and composition between the surface and the bottom of the pits leads to a difference in etch rate and an amplification of the roughness. In addition to this intrinsic roughening mechanism, the presence of a metallic mask (titanium nitride) can lead to an extrinsic roughening mechanism, such as micromasking caused by metallic particles originating form the titanium nitride mask.

A new technique, so called “scatterometric porosimetry” (SP) has been developed to improve our knowledge on the properties of porous material patterned structures. None of the existing techniques is able to characterize the porous material structures after patterning. SP is based on the measurement of the refractive index variation of porous material structures (lines and holes) when filled with a solvent (toluene, methanol, and water). This technique is applied to monitor the modifications in low-K dielectric materials (porous SiOCH) after the plasma patterning steps used to form lines and vias in the porous materials in a typical dual damascene CMOS technology process.

H 2 , O 2 , NH 3 and CH 4 in situ post-etching treatments (PET) have been investigated as a solution to prevent the residues formation (TiFx based) on TiN metallic hard mask (MHM) after etching in fluorocarbon based plasmas. The PET impact on the residues growth reduction on the mask and on the porous SiOCH modification is presented and discussed. The compatibility of the different PET is also evaluated for C045 dual damascene level using trench first MHM integration.

Porous ultra low‐κ (ULK) dielectrics are used to reduce resistance‐capacitance delay for advanced CMOS interconnects. Since the porosity leads to an increased sensitivity of the material to cleaning, etching and ashing plasmas, new characterization techniques are needed to assess the ULK properties during its integration. We show that ellipsometric porosimetry (EP), especially with the combination of several solvents, can be successfully used to characterize porous SiOCH films after different plasma treatments, using reducing and oxidizing chemistries (NH3, H2, CH4 or O2). The characterization of the plasma modified layer is presented and discussed in terms of thickness, hydrophobicity (EP and water contact angle) and κ value. In addition, infrared spectroscopy is used to quantify the methyl (Si‐CH3) depletion. Finally the plasma sealing efficiency is quantified by studying the solvent penetration kinetics.

International audience; For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, …) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO2 hard mask may lead to severe profile distortions, attributed to TiFx compounds which settle on the trenches sidewalls. A chuck temperature of 60 °C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.

A new process, based on the interaction between Si and N rich gas cluster and post Cu CMP features surface, was integrated in a multi-level Cu interconnect stack using 65 nm design rules. Using the same integration scheme as stand-alone SiCN dielectric capping, excellent electrical properties were achieved when the process was implemented with a USG layer on top of a porous Ultra-Low K. Furthermore, 3x electromigration time to failure improvement was evidenced, making the approach very promising to address EM performance requirement for the most advanced technology nodes. Moreover, contrary to PE-CVD CuSiN approach, the process does not depend on Cu crystallographic orientation. Finally, when the implantation process is performed on un-capped ULK, a deep N contamination occurs. Therefore, the process must be optimized to preserve the interest of this technique for the most aggressive architectures.

Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (