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146 results on '"Quinones, Eduardo"'

1. Integrating supervised and reinforcement learning for predictive control with an unmodulated pyramid wavefront sensor for adaptive optics

Author

Pou, Bartomeu, Smith, Jeffrey, Quinones, Eduardo, Martin, Mario, and Gratadour, Damien

Subjects
Astrophysics - Instrumentation and Methods for Astrophysics
Abstract

We propose a novel control approach that combines offline supervised learning to address the challenges posed by non-linear phase reconstruction using unmodulated pyramid wavefront sensors (P-WFS) and online reinforcement learning for predictive control. The control approach uses a high-order P-WFS to drive a tip-tilt stage and a high-dimensional mirror concurrently. Simulation results demonstrate that our method outperforms traditional control techniques, showing significant improvements in performance under challenging conditions such as faint stars and poor seeing, and exhibits robustness against variations in atmospheric conditions.

Published
2024

2. Event-Based OpenMP Tasks for Time-Sensitive GPU-Accelerated Systems

Author

Cetre, Cyril, Yu, Chenle, Royuela, Sara, Barrere, Rémi, Quiñones, Eduardo, Gratadour, Damien, Goos, Gerhard, Series Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Espinosa, Alexis, editor, Klemm, Michael, editor, de Supinski, Bronis R., editor, Cytowski, Maciej, editor, and Klinkenberg, Jannis, editor

Published
2024
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3. Taskgraph: A Low Contention OpenMP Tasking Framework

Author

Yu, Chenle, Royuela, Sara, and Quiñones, Eduardo

Subjects
Computer Science - Distributed, Parallel, and Cluster Computing
Abstract

OpenMP is the de-facto standard for shared memory systems in High-Performance Computing (HPC). It includes a task-based model that offers a high-level of abstraction to effectively exploit highly dynamic structured and unstructured parallelism in an easy and flexible way. Unfortunately, the run-time overheads introduced to manage tasks are (very) high in most common OpenMP frameworks (e.g., GCC, LLVM), which defeats the potential benefits of the tasking model, and makes it suitable for coarse-grained tasks only. This paper presents taskgraph, a framework that uses a task dependency graph (TDG) to represent a region of code implemented with OpenMP tasks in order to reduce the run-time overheads associated with the management of tasks, i.e., contention and parallel orchestration, including task creation and synchronization. The TDG avoids the overheads related to the resolution of task dependencies and greatly reduces those deriving from the accesses to shared resources. Moreover, the taskgraph framework introduces in OpenMP the record-and-replay execution model that accelerates the taskgraph region from its second execution. Overall, the multiple optimizations presented in this paper allow exploiting fine-grained OpenMP tasks to cope with the trend in current applications pointing to leverage massive on-node parallelism, fine-grained and dynamic scheduling paradigms. The framework is implemented on LLVM 15.0. Results show that the taskgraph implementation outperforms the vanilla OpenMP system in terms of performance and scalability, for all structured and unstructured parallelism, and considering coarse and fine grained tasks. Furthermore, the proposed framework considerably reduces the performance gap between the task and the thread models of OpenMP.

Published
2022

6. A Low Overhead Tasking Model for OpenMP

Author

Yu, Chenle, Royuela, Sara, Quiñones, Eduardo, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Chaves, Ricardo, editor, B. Heras, Dora, editor, Ilic, Aleksandar, editor, Unat, Didem, editor, Badia, Rosa M., editor, Bracciali, Andrea, editor, Diehl, Patrick, editor, Dubey, Anshu, editor, Sangyoon, Oh, editor, L. Scott, Stephen, editor, and Ricci, Laura, editor

Published
2022
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7. The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision Ready to Exploit Heterogeneous HPC and Cloud Architectures

Author

Aldinucci, Marco, Atienza, David, Bolelli, Federico, Caballero, Mónica, Colonnelli, Iacopo, Flich, José, Gómez, Jon A., González, David, Grana, Costantino, Grangetto, Marco, Leo, Simone, López, Pedro, Oniga, Dana, Paredes, Roberto, Pireddu, Luca, Quiñones, Eduardo, Silva, Tatiana, Tartaglione, Enzo, Zapater, Marina, Curry, Edward, editor, Auer, Sören, editor, Berre, Arne J., editor, Metzger, Andreas, editor, Perez, Maria S., editor, and Zillner, Sonja, editor

Published
2022
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8. Distributed Big Data Analytics in a Smart City

Author

Serrano, Maria A., Hadad, Erez, Cavicchioli, Roberto, Palmero, Rut, Chiantore, Luca, Amendola, Danilo, Quiñones, Eduardo, Curry, Edward, editor, Auer, Sören, editor, Berre, Arne J., editor, Metzger, Andreas, editor, Perez, Maria S., editor, and Zillner, Sonja, editor

Published
2022
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11. Enhancing OpenMP Tasking Model: Performance and Portability

Author

Yu, Chenle, Royuela, Sara, Quiñones, Eduardo, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, McIntosh-Smith, Simon, editor, de Supinski, Bronis R., editor, and Klinkenberg, Jannis, editor

Published
2021
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12. Distributed Training on a Highly Heterogeneous HPC System

Author

Flich, Jose, Hernandez, Carles, Quiñones, Eduardo, Paredes, Roberto, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Orailoglu, Alex, editor, Jung, Matthias, editor, and Reichenbach, Marc, editor

Published
2020
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13. Static Analysis to Enhance Programmability and Performance in OmpSs-2

Author

Munera, Adrian, Royuela, Sara, Ferrer, Roger, Peñacoba, Raul, Quiñones, Eduardo, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Jagode, Heike, editor, Anzt, Hartwig, editor, Juckeland, Guido, editor, and Ltaief, Hatem, editor

Published
2020
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14. The Cooperative Parallel: A Discussion About Run-Time Schedulers for Nested Parallelism

Author

Royuela, Sara, Serrano, Maria A., Garcia-Gasulla, Marta, Mateo Bellido, Sergi, Labarta, Jesús, Quiñones, Eduardo, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Fan, Xing, editor, de Supinski, Bronis R., editor, Sinnen, Oliver, editor, and Giacaman, Nasser, editor

Published
2019
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16. Towards an OpenMP Specification for Critical Real-Time Systems

Author

Serrano, Maria A., Royuela, Sara, Quiñones, Eduardo, Hutchison, David, Series Editor, Kanade, Takeo, Series Editor, Kittler, Josef, Series Editor, Kleinberg, Jon M., Series Editor, Mattern, Friedemann, Series Editor, Mitchell, John C., Series Editor, Naor, Moni, Series Editor, Pandu Rangan, C., Series Editor, Steffen, Bernhard, Series Editor, Terzopoulos, Demetri, Series Editor, Tygar, Doug, Series Editor, Weikum, Gerhard, Series Editor, de Supinski, Bronis R., editor, Valero-Lara, Pedro, editor, Martorell, Xavier, editor, Mateo Bellido, Sergi, editor, and Labarta, Jesus, editor

Published
2018
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17. Safe Parallelism: Compiler Analysis Techniques for Ada and OpenMP

Author

Royuela, Sara, Martorell, Xavier, Quiñones, Eduardo, Pinho, Luis Miguel, Hutchison, David, Series Editor, Kanade, Takeo, Series Editor, Kittler, Josef, Series Editor, Kleinberg, Jon M., Series Editor, Mattern, Friedemann, Series Editor, Mitchell, John C., Series Editor, Naor, Moni, Series Editor, Pandu Rangan, C., Series Editor, Steffen, Bernhard, Series Editor, Terzopoulos, Demetri, Series Editor, Tygar, Doug, Series Editor, Weikum, Gerhard, Series Editor, Casimiro, António, editor, and Ferreira, Pedro M., editor

Published
2018
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18. A Functional Safety OpenMP for Critical Real-Time Embedded Systems

Author

Royuela, Sara, Duran, Alejandro, Serrano, Maria A., Quiñones, Eduardo, Martorell, Xavier, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, de Supinski, Bronis R., editor, Olivier, Stephen L., editor, Terboven, Christian, editor, Chapman, Barbara M., editor, and Müller, Matthias S., editor

Published
2017
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19. OpenMP Tasking Model for Ada: Safety and Correctness

Author

Royuela, Sara, Martorell, Xavier, Quiñones, Eduardo, Pinho, Luis Miguel, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Blieberger, Johann, editor, and Bader, Markus, editor

Published
2017
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21. Speeding up Static Probabilistic Timing Analysis

Author

Milutinovic, Suzana, Abella, Jaume, Hardy, Damien, Quiñones, Eduardo, Puaut, Isabelle, Cazorla, Francisco J., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Pinho, Luís Miguel Pinho, editor, Karl, Wolfgang, editor, Cohen, Albert, editor, and Brinkschulte, Uwe, editor

Published
2015
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27. A Non Linear Control Method with Reinforcement Learning for Adaptive Optics with Pyramid Sensors

Author

Pou, Bartomeu, Smith, Jeffrey, Quinones, Eduardo, Martin, Mario, and Gratadour, Damien

Subjects
Adaptive Optics, Reinforcement Learning
Abstract

Extreme Adaptive Optics (AO) systems are designed to provide high resolution and high contrast observing capabilities on the largest ground-based telescopes through exquisite phase reconstruction accuracy. In that context, the pyramid wavefront sensor (P-WFS) has shown promise to deliver the means to provide such accuracy due to its high sensitivity. However, traditional methods cannot leverage the highly non-linear P-WFS measurements to their full potential. We present a predictive control method based on Reinforcement Learning (RL) for AO control with a P-WFS. The proposed approach is data-driven, has no assumptions about the system's evolution, and is non-linear due to the usage of neural networks. First, we discuss the challenges of using an RL control method with a P-WFS and propose solutions. Then, we show that our method outperforms an optimized integrator controller. Finally, we discuss its possible path for an actual implementation.

Published
2022
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29. Taskgraph: A Low Contention OpenMP Tasking Framework

Author

Yu, Chenle, Royuela, Sara, and Quinones, Eduardo

Abstract

OpenMP is the de-facto standard for shared memory systems in High-Performance Computing (HPC). It includes a tasking model that offers a high-level of abstraction to effectively exploit structured (loop-based) and highly dynamic unstructured (task-based) parallelism in an easy and flexible way. Unfortunately, the run-time overheads introduced to manage tasks are (very) high in most common OpenMP frameworks (e.g., GCC, LLVM), which defeats the potential benefits of the tasking model, and makes it suitable for coarse-grained tasks only. This paper presents taskgraph, a framework that uses a task dependency graph (TDG) to represent a region of code implemented with OpenMP tasks in order to reduce the run-time overheads associated with the management of tasks, i.e., contention and parallel orchestration, including task creation and synchronization. The TDG avoids the overheads related to the resolution of task dependencies and greatly reduces those deriving from accesses to shared resources. Moreover, the taskgraph framework introduces in OpenMP the record-and-replay execution model that accelerates the taskgraph region from its second execution. Overall, the multiple optimizations presented in this paper allow exploiting fine-grained OpenMP tasks to cope with the trend in current applications pointing to leverage massive on-node parallelism, fine-grained and dynamic scheduling paradigms. The framework is implemented on LLVM 15.0. Results show that the taskgraph implementation outperforms the vanilla OpenMP system in terms of performance and scalability, for all structured and unstructured parallelism, and considering coarse and fine grained tasks. Furthermore, the proposed framework makes the tasking model a competitive alternative to the OpenMP thread model in most cases.

Published
2023
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30. The AMPERE Project: : A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization

Author

Quinones, Eduardo, primary, Royuela, Sara, additional, Scordino, Claudio, additional, Gai, Paolo, additional, Pinho, Luis Miguel, additional, Nogueira, Luis, additional, Rollo, Jan, additional, Cucinotta, Tommaso, additional, Biondi, Alessandro, additional, Hamann, Arne, additional, Ziegenbein, Dirk, additional, Saoud, Hadi, additional, Soulat, Romain, additional, Forsberg, Bjorn, additional, Benini, Luca, additional, Mando, Gianluca, additional, and Rucher, Luigi, additional

Published
2020
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32. High Performance Embedded Computing

Author

Pinho, Luis Miguel, Quinones, Eduardo, and Bertogna, Marko

Subjects
Computer architecture and logic design, Energy, bic Book Industry Communication::U Computing & information technology::UY Computer science::UYF Computer architecture & logic design, bic Book Industry Communication::P Mathematics & science::PH Physics::PHD Classical mechanics::PHDY Energy
Abstract

Nowadays, the prevalence of computing systems in our lives is so ubiquitous that we live in a cyber-physical world dominated by computer systems, from pacemakers to cars and airplanes. These systems demand for more computational performance to process large amounts of data from multiple data sources with guaranteed processing times. Actuating outside of the required timing bounds may cause the failure of the system, being vital for systems like planes, cars, business monitoring, e-trading, etc. High-Performance and Time-Predictable Embedded Computing presents recent advances in software architecture and tools to support such complex systems, enabling the design of embedded computing devices which are able to deliver high-performance whilst guaranteeing the application required timing bounds. Technical topics discussed in the book include:  Parallel embedded platforms Programming models Mapping and scheduling of parallel computations Timing and schedulability analysis Runtimes and operating systemsThe work reflected in this book was done in the scope of the European project P SOCRATES, funded under the FP7 framework program of the European Commission. High-performance and time-predictable embedded computing is ideal for personnel in computer/communication/embedded industries as well as academic staff and master/research students in computer science, embedded systems, cyber-physical systems and internet-of-things.

Published
2018
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41. Experiences and Results of Parallelisation of Industrial Hard Real-time Applications for the parMERASA Multi-core

Author

Ungerer, Theo, Bradatsch, Christian, Frieb, Martin, Kluge, Florian, Mische, Jörg, Stegmeier, Alexander, Jahr, Ralf, Gerdes, Mike, Zaykov, Pavel, Matusova, Lucie, Li, Zai Jian Jia, Petrov, Zlatko, Böddeker, Bert, Kehr, Sebastian, Regler, Hans, Hugl, Andreas, Rochange, Christine, Ozaktas, Haluk, Cassé, Hugues, Bonenfant, Armelle, Sainrat, Pascal, Lay, Nick, George, David, Broster, Ian, Quinones, Eduardo, Panic, Milos, Abella, Jaume, Hernandez, Carles, Cazorla, Francisco, Uhrig, Sascha, Rohde, Mathias, Pyka, Arthur, University of Augsburg (UNIA), Institute of Computer Science - University of Augsburg (ICS), Universität Augsburg [Augsburg], Honeywell International S.r.o. [Prague], DENSO AUTOMOTIVE Deutschland, Bauer Group (GERMANY), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Université Toulouse III - Paul Sabatier (UT3), Rapita Systems Ltd [York], Rapida Systems, Barcelona Supercomputing Center - Centro Nacional de Supercomputacion (BSC - CNS), Technische Universität Dortmund [Dortmund] (TU), Luís Miguel Pinho, CISTER, Portugal, Eduardo Quiñones, BSC, Spain, Sascha Uhrig, TU Dortmund, Germany, HiPEAC : European Network on High-performance Embedded Architecture and Compilation, European Project: 287519, Grélaud, Françoise, European Union Seventh Framework Programme - 287519 - INCOMING, University of Augsburg [Augsburg], Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs]
Abstract

International audience; The EC FP-7 project parMERASA (Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability, Oct. 1, 2011 until Sept. 30, 2014) provides a timing analysable system of parallel hard real-time applications running on a scalable multi-core processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelising hard real-time programs to run on predictable multi-/many-core processors. A software engineering approach was developed to ease sequential to parallel program transformation by developing and supporting suitable parallel design patterns that are analysable. The following sequential hard real-time programs were parallelised by applying the pattern-oriented parallelisation approach: 3D path planning and stereo navigation algorithms (Honeywell International s.r.o.), diesel engine management system (DENSO AUTOMOTIVE Deutschland GmbH), and the control algorithm for a dynamic compaction machine (BAUER Maschinen GmbH). The paper reports on parallelisation approach, experiences made during parallelisation with applications, tools and multi-core architecture, scalability of applications and quantitative results reached.

Published
2015

42. Measurement-Based Timing Analysis of the AURIX Caches

Author

Kosmidis, Leonidas, Compagnin, Davide, Morales, David, Mezzetti, Enrico, Quinones, Eduardo, Abella, Jaume, Vardanega, Tullio, Cazorla, Francisco J., Kosmidis, Leonidas, Compagnin, Davide, Morales, David, Mezzetti, Enrico, Quinones, Eduardo, Abella, Jaume, Vardanega, Tullio, and Cazorla, Francisco J.

Abstract

Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has caused a large fraction of real-time systems industry to avoid using them, especially in the automotive sector. For measurement-based timing analysis (MBTA) - the dominant technique in domains such as automotive - cache challenges the definition of test scenarios stressful enough to produce (cache) layouts that causing high contention. In this paper, we present our experience in enabling the use of caches for a real automotive application running on an AURIX multiprocessor, using software randomization and measurement-based probabilistic timing analysis (MBPTA). Our results show that software randomization successfully exposes - in the experiments performed for timing analysis - cache related variability, in a manner that can be effectively captured by MBPTA.

Published
2016
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43. Measurement-Based Timing Analysis of the AURIX Caches

Author

Leonidas Kosmidis and Davide Compagnin and David Morales and Enrico Mezzetti and Eduardo Quinones and Jaume Abella and Tullio Vardanega and Francisco J. Cazorla, Kosmidis, Leonidas, Compagnin, Davide, Morales, David, Mezzetti, Enrico, Quinones, Eduardo, Abella, Jaume, Vardanega, Tullio, Cazorla, Francisco J., Leonidas Kosmidis and Davide Compagnin and David Morales and Enrico Mezzetti and Eduardo Quinones and Jaume Abella and Tullio Vardanega and Francisco J. Cazorla, Kosmidis, Leonidas, Compagnin, Davide, Morales, David, Mezzetti, Enrico, Quinones, Eduardo, Abella, Jaume, Vardanega, Tullio, and Cazorla, Francisco J.

Abstract

Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has caused a large fraction of real-time systems industry to avoid using them, especially in the automotive sector. For measurement-based timing analysis (MBTA) - the dominant technique in domains such as automotive - cache challenges the definition of test scenarios stressful enough to produce (cache) layouts that causing high contention. In this paper, we present our experience in enabling the use of caches for a real automotive application running on an AURIX multiprocessor, using software randomization and measurement-based probabilistic timing analysis (MBPTA). Our results show that software randomization successfully exposes - in the experiments performed for timing analysis - cache related variability, in a manner that can be effectively captured by MBPTA.

Published
2016
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45. PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis

Author

Cazorla, Francisco J., primary, Abella, Jaume, additional, Andersson, Jan, additional, Vardanega, Tullio, additional, Vatrinet, Francis, additional, Bate, Iain, additional, Broster, Ian, additional, Azkarate-Askasua, Mikel, additional, Wartel, Franck, additional, Cucu, Liliana, additional, Cros, Fabrice, additional, Farrall, Glenn, additional, Gogonel, Adriana, additional, Gianarro, Andrea, additional, Triquet, Benoit, additional, Hernandez, Carles, additional, Lo, Code, additional, Maxim, Cristian, additional, Morales, David, additional, Quinones, Eduardo, additional, Mezzetti, Enrico, additional, Kosmidis, Leonidas, additional, Aguirre, Irune, additional, Fernandez, Mikel, additional, Slijepcevic, Mladen, additional, Conmy, Philippa, additional, and Talaboulma, Walid, additional

Published
2016
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